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SRC proposes standardised testing for 3D chips

15 Apr 2015  | R. Colin Johnson

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The aggregated measurements made for DFT-made TSVs does not tell you exactly where any defects lie, but it does tell you that defects are present, and that this die or stack of dies should be rejected. Plus it can be performed very quickly since multiple TSVs are probed simultaneously.

3D stacked chips

3D stacked chips can theoretically be used any number of chips connected TSVs. (Source: Duke University)

"Our research demonstrates that normal probe cards can be used for 3D chips to detect both process variations as well as bad die," indicated Chakrabarty.

Chakrabarty's team at Duke has also studied how to recover the DFT overhead during 3D chip stacking tests by using retiming that redistributes that slack on critical paths, thus reducing overhead for using DFTs at all.

3D stacked chips are connected by copper via terminated in microbumps

3D stacked chips are connected by copper via terminated in microbumps. (Source: Duke University)

Assisting on the project was Brandon Noia, a doctoral candidates who was part of the Duke team and a recipient of the SRC Ph.D. Fellowship. Now graduated and part of SRC member company, AMD, Noia also received the European Design and Automation Association 2014 Outstanding Dissertation Award for this research.

Duke is collaborating with electronic design automation (EDA) companies with at least one company prepared to have measurement data on chips available this fall.

Members of SRC that have free access to this technology include GlobalFoundries, IBM, Intel, Freescale, Texas Instruments, Advanced Micro Devices, Analog Devices and Qualcomm, and Mubadala Technology. Funding was provided by the Texas Analog Centre of Excellence, SRC and the University of Illinois.

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