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TI's multi-processor sol'n leaves FPGAs in the dust

23 Apr 2015  | R. Colin Johnson

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Texas Instruments (TI) has rolled out a multi-processor solution that promises to up the ante in terms of downsizing, targeting massive avionic, military, test and measurement and medical instruments, from backpack radars to portable magnetic resonance instruments (MRIs). According to TI, the Keystone-II (66AK2L06) solution allows devices using it to be 66 per cent smaller, use 60 per cent less power, cost 50 per cent less and are three times faster to market than using an FPGA solution.

"Our newest Keystone II SoC has two ARM Cortex A15 MPCore processors, four 1.2GHz C66x DSPs and four programmable accelerators," said Robert Ferguson, communications processors business development manager at TI.

Keystone-II (66AK2L06) solution

TI's FPGA-killer is an SoC with two ARM cores, four DSPs and four programmable hardware accelerators all connected by TeraNet on-chip and by four lanes of 7.8Gb JESD204B interfaces off-chip. (Source: TI)

That spells significant system-level savings for high-speed data acquisition when paired with 4-lanes of JEDEC-compatible input/output (I/O) running at 7.3Gb/s per lane (JESD204B).

The four on-chip accelerators are connected to the other six cores, and each other, with TI's on-chip TeraNet. The four accelerators include a programmable digital-radio front-end (DFE), two programmable Fast Fourier Transform coprocessors (FFTCs), a programmable security accelerator for high-speed encryption/decryption and a packet accelerator for network coprocessor (NETCP) for operations such as header matching and packet modification operations, connected to four gigabit Ethernet (GbE) modules to send and receive packets.

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