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Security architecture for automotive MCU flash memory

06 May 2015  | Yash Saini, Satyam Shandilya, Arun Jain

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b) Partitioning flash memory array into secure and non-secure regions
Flash memory array can be partitioned into secured and non-secured regions. The secured region can be used to store critical data. Non-secured flash partitions can be mapped to the main interface. And the secured flash partitions can be mapped to the alternate interface.

Flash controller can route the trusted masters to the alternate interface, and thereby allow them to access secured region.

Figure 3: Partitioning flash memory array into secure and non-secure regions.

c) Intelligent arbiter in flash controller
Flash controllers can contain an arbitration logic whose main function is to provide arbitration among the masters when they are accessing the flash memory simultaneously. So every master must possess a unique master identification number to help the flash controller to differentiate between the masters. The Master ID can be used to differentiate between trusted and non-trusted master. Hence a non-trusted master accessing the part of flash, which is meant only for a trusted master, can be restricted by the controller.

Figure 4: Intelligent arbiter in flash controller.

To ensure the reliability of the vehicle, it has become extremely important to ensure that code resides in a secured memory region to avoid malfunctioning of the system. Security has become a key driving factor for the automotive industry, for supplier and OEM to meet the stringent safety requirements. The architectures here present ways in which data security in an SoC can be achieved.

About the authors
Yash Saini is a Design Engineer at Freescale Semiconductors (Noida, India Design Center), working in the Automotive and Industrial Solution Group (AISG) for over a year. He graduated from Malaviya National Institute Of Technology and has worked on multiple SoCs in front-end Verification and Post-Si Validation, with areas of interests being low power designs and safety & Security architectures.

Satyam Shandilya works as a SoC Verification Engineer at Freescale Semiconductors for more than two years now. He obtained B.Tech in E.C.E from National Institute of Technology, Kurukshetra in 2012. His areas of interests includes Security, CODECs and Digital VLSI design.

Arun Jain is the Lead Design Engineer with Freescale Semiconductors. He has over six years of experience in semiconductor industry. He has been involved in SoC development, verification and validation for Mobile and Automotive Industry. He has completed B.Tech from IIT Kanpur.

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