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ST sets Power Architecture at core of car safety

11 May 2015  | Bernard Cole

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The mid-1980s saw the debut of the Power Architecture in IBM's mainframe computers. Moving a little bit towards the future, the PowerPC, a variation of the original Power Architecture, lost out in desktop computing when Apple switched to the x86 in its MacIntosh desktop computer. Contrary to what you probably have in mind, the technology still lives, and may even outlive Moore's Law.

The architecture still maintains a leading position in supercomputing, high-end servers, and routers. But it's fighting for market share there with the x86 and MIPS architectures, and, most recently, high-end ARM variants.

However, it currently has an almost unassailable position, and will have for the next several decades, in high-end embedded apps in the automotive power train, body electronics, chassis and safety subsystems.

According to Roger Forchhammer, senior marketing and system architect manager at STMicroelectronics, a small part of the Power Architecture's rock solid position there is due to the decades-long product life cycles of electronics in the automobile industry. Beyond that, he said its longevity has more to do with the fact that the architecture and instruction set of the Power CPU is ideally suited for the kind of real-time, deterministic, and reliable fail-safe operation that the automotive power train requires.

In short, automotive systems engineers know a good thing when they see it and are reluctant to give it up.

"ST has some original implementations of the Power Architecture in automobiles that go back decades and we are still generating substantial business from them," Forchhammer said. "Projecting ahead, it is not too unreasonable to assume that the Power Architecture will be in the power train and body electronics of autos for some time to come."

ST's Automotive Power CPU roadmap

ST's Automotive Power CPU roadmap calls for 28nm by 2017.

A good measure of ST's commitment to the Power Architecture is the company's current 2011-2017 roadmap for the 32bit MCUs it plans for this segment of the auto market. From 90nm in 2011, its automotive power MCUs have been scaled down to 40nm and will go to 28nm within two years. Forchhammer said that with each scaling to smaller geometries, the company will continue to add features that further improve the architecture's capabilities in not only the power train, but the body electronics and ADAS.

For example, ST's recently announced 40nm SPC58NF family architecture combines multiple high-performance cores with up to 6MB Flash and 768KB internal RAM memory, eight CAN interfaces, and an optimised peripheral set based on the end application.

Power Architecture in ST's power train MPUs

Current SPC58NF implementation of Power Architecture in ST's power train MPUs incorporates extensive safety and security features.

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