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Mitigating SEU using isolated design flow (Part 1)

19 May 2015  | Rajan Bedi

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To partition floor-planned logic, a fence (isolated region) is necessary to separate them. The fence is not specifically drawn as it is what is left over between blocks, i.e. unused tiles in which no routing or logic is present. Fences may comprise CLBs, BRAM, DSP, I/O blocks, GTX transceivers etc. as shown in figure 2.


Figure 2: Isolated functions are separated by a fence of unused logic tiles. (Image courtesy of Xilinx).


The partitioned floor-plan of a single-chip, cryptographic design comprising two, redundant, AES-encryption modules and its subsequent implementation are shown in figure 3 and figure 4.


Figure 3: The partitioned floor-plan of a single-chip, cryptographic design comprising two, redundant, AES-encryption modules is shown here. (Image courtesy of Xilinx).




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