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Clocking wideband GSPS analogue to digital converters

20 May 2015  | Ian Beavers

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As high speed signal acquisition applications using multiple analogue to digital converters (ADCs) increase in complexity, each converter's complementary clock solution will dictate the dynamic range and capacity of the system's potential. With the increase in sample rate and input bandwidth of emerging Giga-Sample per Second (GSPS) ADCs, the capability and performance of the system's distributed sample clock becomes critical. System solutions that target high frequency measurements, such as electrical measurement instrumentation and multi-converter array applications will need leading edge clocking solutions.

Focused selection of the companion clock solution is important to prevent limitation of the ADC's dynamic range. Depending upon the input bandwidth and frequency of interest, the clock jitter can otherwise limit the performance of the ADC. Low jitter and phase noise, distribution de-skew and alignment capabilities for the converter's high speed JESD204B serial interface are all clocking attributes that become paramount for optimum system performance.

Multiple channel low jitter GHz clock solutions that support ADCs with JESD204B outputs continue to proliferate in the industry. We get questions from design engineers about how to select the right clock solution for their GSPS ADCs. Below are answers and analysis to some common discussions regarding the technical impact of pairing a clock solution with a particular ADC.

Using high input frequencies to wideband GSPS ADCs in the 2nd or 3rd Nyquist zone requires lower jitter, high speed clocks. What is the impact of clock jitter on my ADC's performance?

As higher frequency input signals are used in systems with the adoption of GSPS ADCs and direct RF sampling, the impact of clock jitter on the system performance becomes more critical. A fixed amount of clock jitter may not impose any limitations on system performance with low frequency inputs. As ADC input frequencies increase, the same fixed amount of clock jitter will eventually have an impact on the Signal to Noise Ratio (SNR) of the system. The SNR from an ADC is defined as the log ratio of the signal power to the total non-signal power, or noise, that is seen at the input to the ADC.

The ADC sample instant with a known amount of clock jitter will create a larger or more ambiguous sample voltage delta (dV) when sampling a faster rise time signal at a higher frequency. This is due to the faster slew rate of higher frequency signals as compared to lower frequency signals. An example of this can be seen in figure 1.

Figure 1: With a fixed amount of encode jitter (dt) seen at the ADC clock, a higher frequency input signal will have a larger sampled voltage error (dV) relative to a lower frequency input signal. This will have a direct impact on the dynamic range capability of the ADC.

What is the difference between peak-to-peak and RMS (root mean squared) jitter?

There are two categories of jitter on a clock signal that can impact an ADC's performance, random jitter (RJ) and deterministic jitter (DJ). Deterministic jitter comes from an identifiable interference signal and has an amplitude that is bounded in magnitude. It is created by all other unwanted signal characteristics such as crosstalk, Electromagnetic Interference (EMI) radiation, supply noise, and periodic modulation such as simultaneous switching. Deterministic jitter will appear as spurious signals on the clock signal. These unwanted signals will also show up as spurious on the digitized spectrum from the ADC.

Random jitter is unbounded and Gaussian in magnitude. It can be created by influences that are less predictable such as temperature and small semiconductor process variations. If there is enough random jitter present on an ADC sample clock, it may raise the Noise Spectral Density (NSD) power on the data converter. The magnitude of each RJ and DJ root square summed (RSS) together will determine the total jitter impact on the ADC sample clock.

A histogram of the random jitter magnitude on a typical clock signal should have a purely normal Gaussian distribution. Any additional deterministic component to the jitter will create a bi-modal distribution. Peak-to-peak jitter is measured by taking a large population of timing measurements and determining the absolute smallest and largest jitter variation. As more measurements are taken, the minimum and maximum jitter will eventually continue to expand the absolute peak-to-peak value. A practical measurement must be bounded at some point in time and measurement sample quantity. Therefore, an absolute peak-to-peak jitter value is not particularly useful, unless it is based on a Gaussian distribution with a known standard deviation.

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