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Clocking wideband GSPS analogue to digital converters

20 May 2015  | Ian Beavers

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The RMS jitter is the value of one standard deviation within a Gaussian plot. This value will stay relatively stable, even as the measured sample size increases. It also makes the RMS jitter value more meaningful than the peak-to-peak jitter and easier to measure. For the RMS jitter to have a meaningful magnitude, the total jitter must have a Gaussian profile. Otherwise, a distorted Gaussian profile will identify that a deterministic jitter component is present. If possible, the root cause of the deterministic jitter component should be identified and mitigated or removed.

Figure 2: Although an ideal clock signal would have all of its power reside in a single frequency bin, real world clock solutions will have some magnitude of 'phase noise skirt'. A clock signal with only random jitter will form a Gaussian distribution. Any deterministic jitter will distort the ideal Gaussian profile. The phase noise power at any point on the curve can be measured from its peak at F0 to a frequency bin of interest at F0 + Fm.

How can the SNR and NSD be degraded by the ADC's input clock jitter?

An ADC's NSD is one of the main performance metrics of a converter. NSD defines the entire noise power, per unit of bandwidth, sampled at the corresponding ADC sample frequency (Fs). NSD is a function of the Full Scale Signal to Noise Ratio (SNRFS) of an ADC, with any clock jitter degradation, and the Nyquist bandwidth (Fs/2) in which the noise is spread across the spectrum. Any sampling instant error will degrade some portion of the signal power to noise.

As clock jitter increases, some portion of the sampled signal power of interest is spread outside of its discrete frequency bin in a Fast Fourier Transform (FFT) and subsequently becomes part of the noise power. This is due to the non-ideal sampling instant of the signal by the phase noise of the clock signal. Figure 2 shows a visual example of how phase noise 'skirts' bleed off power from the desired signal of interest in the frequency domain.

Figure 3: Ideal NSD performance for an ADC operating at 1GSPS limited by its RMS encode clock jitter. The RMS jitter of the clock can limit the ADCs dynamic range at higher input frequencies.

To find the total SNR degradation of an ADC, compute the root sum square of the jitter noise power and the published SNR of the ADC at the signal frequency of interest. When the ADC sampling clock jitter is sufficiently low, the SNRadc = SNRdegradation as the internal aperture jitter and non-linearities of the converter will limit its SNR. Conversely, a sampling clock with increasing jitter will eventually become the limiting factor in the SNR performance of the ADC. This will be more pronounced as the signal of interest is higher in frequency. Output noise for all realisable ADCs is limited by its SNR performance. As input level is increased or decreased, the jitter noise component changes accordingly.

The NSD of the ADC can be computed based on the full scale input power to the ADC minus the SNR degradation and the noise power, which is a function of the Nyquist rate. This can be seen in the equation below.

NSDADC= PowerADC_FS- SNRdegradation(dBFS) – 10log(Fs/2)

Figure 4: This plot shows a 14b wideband converter that is limited to an NSD of -155dBFS/Hz at low (<100MHz) analogue input frequencies by the internal ADC quantisation, and linearity, regardless of external RMS clock jitter up to 200fs. In this case, the system clock jitter will dictate NSD performance at higher analogue input frequencies (>100MHz) depending upon its RMS magnitude.

As an example, figure 4 shows the NSD impact of a 14b 1GSPS ADC, with various clock jitter, across a wide input bandwidth. When sampling a signal from 10 – 100MHz, even a relatively high clock jitter of 200 femto-seconds will not appreciably impair the ADC's NSD performance of -155dBFS/Hz. However, when sampling a 1GHz or 2GHz input signal, the same 200fs RMS jitter of the clock will significantly limit the ADC performance when compared to lower RMS clock jitter. When sampling a 2GHz signal, an RMS jitter of 200fs will have a 12dB increase in the ADC noise, relative to the signal power of interest, compared to an RMS clock jitter of 50fs.

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