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Software tool helps solve dynamic power issues

28 May 2015  | R. Colin Johnson

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To process those gigantic files Mentor has been working to integrate Veloce Power Application with ANSYS's PowerArtist to generate and analyse the fast signal database as it is produced in one step. The result is an activity plot over billions of cycles that identifies activity peaks, allowing the designer to go back to register-transfer level (RTL) and gate-level redesign of the SoC to lower power consumption before going the fab. In the last figure, see the two-to-four times run-time performance improvements achieved for each different block of an SoC.

Veloce Power Application

For a more detailed analysis, see Mentor's white paper or get a demonstration at the Design Automation Conference 2015 (DAC, June 7-11, San Francisco) booth 1432.

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