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New method offers accurate power estimation of SoC designs

03 Jun 2015  | Lauro Rizzatti

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New tools are enabling accurate gate-level power analysis process and a complete RTL power exploration with the elimination of a file-based flow.

In a recent post, I highlighted the intrinsic limitations of the current approach to estimate dynamic power consumption. Briefly, the approach consists of a file-based flow that evolves through two steps. First, a simulator or an emulator tracks the switching activity, either cumulatively for the entire run in a switching activity interchange format (SAIF) file, or on a cycle-by-cycle basis for each signal in a fast signal database (FSDB) file. Later, a power estimation tool fed with a SAIF file calculates the average power consumption of the whole circuit, or an FSDB file is used to compute the peak power in time and space of the design (see Figure 1).

Conventional power analysis

Figure 1: Conventional power analysis is grounded in a two-step, file-based approach.

These techniques may be acceptable when the design-under-test (DUT) is relatively small—in a ball-park of a few million gates or less—and the analysis is performed within a limited time window of up to a million or so clock cycles. Such time windows are typical when the DUT is tested with adaptive functional testbenches.

However, when applied to one of today's large SoC designs boasting tens or hundreds of millions of gates executing embedded software—such as booting an operating system and running application programs that require billions of cycles, for example—three problems defeat the conventional approach:

  1. The sizes of SAIF and, even more do, FSDB files become massive and unmanageable.
  2. The file generation process slows to a crawl that extends to hours, possibly exceeding a day.
  3. File loading into a power estimation tool can extend to several days, possible a week or more.

It seems like a lost cause.

But things changed on May 27, 2015, when Mentor Graphics announced the Veloce Power Application—a software package with the Veloce Activity Plot and the Dynamic Read Waveform application programming interface (API) that sits on top of the Veloce OS3 (see Figure 2).


Figure 2: An OS shields any application from the underling hardware emulator.

The Veloce Power Application addresses the core problems affecting the conventional (and controversial) approach to estimate power consumption. It eliminates the two-step, file-based flow by tightly integrating the Veloce emulator to the power analysis tool.

Design teams no longer have giant files to contend with. That is, no more wasted space, and no more lost days in file creation and file loading. The new approach provides a fast, clean and very effective method to quickly and thoroughly estimate the power consumption of a modern SoC design.

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