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Verify analogue IP with structural netlist

19 Jun 2015  | Naveen Srivastava, Rohit Ranjan, Amit Bathla

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2. Another area, where behavioural models fail to provide a proper modelling, is of the voltages of the Analogue IPs that are generally exposed to the outer world for testing purposes through test signals. In case of behavioural models, these signals are declared as ports and are left in high 'Z' state. Due to this, the only aspect that could be verified using behavioural models is the connectivity of these ports to the test pads. On the contrary, in the structural netlist model, the voltage values are also modelled. For example, VDD is modelled as 1 and ground is modelled as 0. This added information in the structural netlist helps discover some additional defects, which can't be caught using conventional approach.

Here we will discuss one such defect that we encountered during verification of one such analogue IP.

Below is sheet that IP Owner provides for Test Mode Expose Signals:

During simulation using Analogue Behavioural Model, we found out that, in spite of changing values on test_mux_ctrl_vddx, no change was observed on test_dig_out_vddx, since in the behavioural model all voltage signals were modelled as port and left unconnected inside the IP model. As we can observe in below waveform, the test_dig_out_vddx signal is constantly Z throughout the simulation despite of values of test_mux_ctrl_vddx being changed.

Now we will show the simulation results of the structural netlist dumped from SPICE. In this, though we are not able to sense proper voltages, if by chance exposing of signals is wrong, we will be able to capture that abnormality.

3. To quantify the advantage of using structural netlist over behavioural model, we dumped toggle coverage of a test on both database. Results what we got from Structural Netlist were much better than those obtained from traditional behavioural model. Below we will be analysing the results.

Figure 3: Structural Netlist vs. Behavioural Model.

The above approach will result in increased efficiency of the SOC verification team in finding defects in analogue IPs and analogue-digital interfaces. This improves the implementation quality with minimal additional effort, and reduces cycle time as well as R&D cost.

About the authors
Naveen Srivastava and Rohit Ranjan are design engineers.

Amit Bathla works as an SoC Verification Engineer at Freescale Semiconductor India Pvt. Ltd since 2012. He obtained B.Tech in Electronics and Communication Engineering from NIT Kurukshetra in 2012. His areas of interest include VLSI, Robotics and Embedded design.

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