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Altera storage reference design extends data centre lifetime

06 Jul 2015

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Altera Corp. has developed a storage reference design, based on its Arria 10 SoCs, which promises to double the life of NAND flash and can boost the number of programme-erase cycles by up to seven times compared to current NAND flash implementations. According to the company, the reference design includes an Arria 10 SoC with an integrated dual-core ARM Cortex A9 processor, in an optimised, cost-effective, single-chip solution, leveraging a solid-state disk (SSD) controller from Mobiveil and NAND optimisation software from NVMdurance.

This reference design provides improved performance and flexibility in NAND utilisation while reducing the cost of the NAND array by increasing the lifetime of data centre equipment.

Using FPGAs with integrated hard processor systems, designers can quickly take advantage of the cost savings offered by next-generation NAND devices while retaining the flexibility to customise a solution that maximises the performance, durability and storage capacity of their system. This storage solution implements Mobiveil's Universal NVM Express Controller (UNEX), a configurable controller for PCIe-based SSDs, and NVMdurance's NAND flash optimisation software in an Arria 10 SoC, enabling data centres to leverage the most advanced 3D NAND technology without the long design cycles required with ASIC designs.

In this reference design, Mobiveil's controller supports multi-core architectures, enabling threads to run on each core with their own queue and interrupt without any locks required. NVMdurance's NAND flash optimisation software constantly monitors the condition of the NAND flash and automatically adjusts the control parameters in real time, greatly extending the flash system's endurance. The Altera reference design also features end-to-end data protection, encryption and compression, and optimises throughput and power consumption, all in a small silicon footprint.

Altera's NAND storage reference design is available.

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