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Identify SoC pin limitations across packages

16 Jul 2015  | neha srivastava

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Step 3
Finally, we put a formula to AND the return values from previous step for a particular pad for all its Alt modes for a particular package: =AND(CG151,CC151,BY151,BU151,BQ151,BM151,BI151)

A final FALSE means that that pad has a conflict in protocol availability in a particular package for at least one of its Alt modes.

Step 1: Inserting the master table

Steps 2 & 3: Reporting of conflicts in package

Expectation : All VIU functionalities should be available in all the packages.

Conflict : Evident on VIU_DE .

Possible Workaround : VIU_DE is also available on another pad but in that pad it is multiplexed with another VIU functionality itself, ie, the VIU_DATA[23].

Reported to the architecture team .

Clause added in specification: In the lowest package, the full protocol , ie, the 24bit mode of the VIU would not be available.

We are proposing a methodology that can reduce cost, effort and time of analysis, presenting the data in a simplified format conducive to quick deductions.

We are not doing away with analysis , since the onus of the final decision , to mark something as a conflict or not , lies with the person presented with the concise and precise data (primary intended consumer is the SoC Architect) .

For example, if some pad shows conflict, the SoC architect may need to determine if there is provision to provide the conflicting functionality at a second pad to resolve the conflict.

Similarly in case package-wise protocol conflicts are detected, the architecture team may decide to accept a reduced functionality of the protocol or in extreme cases, may go for increasing the pad count or shuffling around the pads.

About the author
Neha Srivastava has been working in the Automotive and Industrial Solution Group (AISG) for seven and a half years now and currently has a designation of lead design engineer at Freescale Semiconductors (Noida, India Design Centre). She has worked on multiple SoCs in front-end verification and verification for testing domain with the areas of interest being low power designs, safety architectures and high performance systems.

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