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Benefits of DDR interface gate-level simulation

11 Aug 2015  | Abhinav Gaur, Kushagra Khorwal

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No matter how advanced static timing analysis (STA) tools become, there are still a lot of advantages to running gate-level simulation (GLS), since it has the capability of uncovering a lot of hidden design issues which are difficult to find in RTL simulations. It gives a clear picture of how the design will behave at the desired frequency with actual delays in place. Hence, although GLS has its own set of challenges (like setup issues, long run time, etc.), it is still very much a part of the sign-off process, and acts as a design-quality confidence booster.

Why GLS is important for DDR memory interface
The JEDEC standard defines a lot of timing parameters for DDR memories which need to be followed for ensuring correct operation. The timing requirements are strict and need to be implemented with a lot of caution. For example, the duty cycle requirement for data strobe signal (commonly known as DQS) is around 45-55%; if this spec gets violated during either write (where the memory controller will drive the strobe signals to the external memory) or read (where the memory drives the strobe signals), then we cannot ensure data sanity. The physical implementation is a challenge in itself since the designer has to take care that there is no deviation from the standard for various timing parameters. The DDR implementation is difficult since it involves a lot of custom procedures also. Hence, we cannot rely solely on STA tools in case of DDR and running GLS becomes a "must" to ensure correct physical implementation of the design. Running GLS for DDR interfaces is challenging, since it involves various testbench setup issues, multiple timing checks, skew checks, various data transfers modes (burst length – 4,8), various standards to conform to (like DDR3, DDR3L, LPDDR2, etc.) and so on.

This paper will try to highlight the various types of issues that can be found by running gate level simulations for DDR, how they can be fixed and implemented correctly in design and what should the Physical Design/STA team do to avoid such type of issues.

Sample issues, challenges and solutions
Duty cycle of clock coming to DDR memory controller
The quality of clock coming to the DDR controller is an important parameter since most of the signals being driven to the external memory by the controller (like DDR clock, data strobes, etc.) are derived from this clock itself.

Generic diagram for a SoC having DDR controller
The duty cycle of clock coming to the external memory should be in the range of 47-53% for ensuring correct operation. If the duty cycle is out of range from the source itself (which is the clock coming to the controller), one is bound to see huge difference between high period and low period of the clock, which can lead to violation of various parameters like tdqsh_min, tdqsl_min, etc. STA has checks for this, but any error; mismatch can lead to write/read failures.

The failure in case of WRITE looks quite apparent but this issue can lead to failure in READ operation as well! It is important to know that during READ, the DQS being driven by the DDR memory is internally derived from the DDR clock it receives. So if the memory is getting a clock having bad duty cycle, the DQS it generates during read can violate specs like read postamble period (trpst), etc.

Hence, the designer must ensure that the path from the clock source (for example – PLL) output to the input of the input clock of the controller should introduce minimum skew in the high and low period of the clock.

Read DQS gating issues
Read DQS gating is a feature wherein the DQS is gated to the read circuit of the controller until a read operation actually starts. This is done to prevent the read FIFOs of the controller from getting corrupted. The read DQS gating is disabled at the beginning of READ and is again enabled at the end of read operation. See below example:

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