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Streamlining SERDES PCB layout: Design Rule Checking

11 Aug 2015  | Patrick Carrier

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Fact: SERDES buses run at much faster speeds than parallel interfaces and are much easier to implement. Fact: These benefits are not without drawbacks.

As long as the high-level architecture of the SERDES interface is sound, a successful implementation of a SERDES bus boils down to "implementation details." Such details must usually be verified by manual inspection of the routed board, but an automated inspection methodology, like that facilitated through the use of design rule checking (DRC), can make the task of reviewing SERDES buses much easier. Here are examples where DRC can be useful:

Targeting differential impedance

SERDES buses are routed with differential traces, which need to be targeted at a specific differential impedance. The target impedance is usually 100Ω differential, but values of 85Ω and 90Ω differential are also quite common. This differential impedance must be maintained along the route to cut reflections and maximise the opening in the eye diagram at the receiver. Impedance discontinuities can come in the form of vias (more on that later), neckdowns in the chip breakout regions, tuning loops to maintain length matching, or any place where the target trace width and/or spacing is changed.

Impedance discontinuities

Figure 1: Impedance discontinuities such as neckdowns in chip breakout regions and tuning loops can occur any place where the target trace width and/or spacing is changed.

Like other rules, a differential impedance DRC needs a number of parameters to allow the rule to be tuned for a specific design. These include a target impedance and tolerance, as well as a minimum length for a violation. Setting a minimum length allows the DRC to ignore impedance discontinuities that are "electrically short" and insignificant to the signals. The default value for this minimum length parameter is 50 mils &mash; which equates to around 8ps flight time on a PCB, roughly 1/6th of a 50ps edge. This allows DRC to ignore marginal non-idealities in the routing, and only report significant impedance discontinuities.

These are different via/pin breakouts that were poorly routed, resulting in a differential impedance violation. Often times, the area beneath an IC will become an "exception area" in the layout, so breakouts like these can frequently occur. Some short discontinuities at a breakout are common and usually acceptable, but the impedance DRC was able to catch these, which were particularly bad. In this case, all of these breakouts can easily be re-routed to meet the impedance target.

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