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Estimate power at RTL to detect problems early

19 Aug 2015  | Aniruddha Gupta, Himani Grover

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RTL power estimation vs. Gate Level Netlist power estimation
The following circuit is taken for the analysis:


 • Synthesis algorithm used at RTL level is different from Gate Level Netlist.
 • At RTL level estimation, area minimisation algorithm is followed. Therefore, the area of the cell picked at RTL synthesis is less as compared with actual netlist.
 • At netlist level, leakage power minimisation algorithm is followed. Therefore, the leakage power of cell picked at RTL synthesis is more as compared with actual netlist.
When compared with power estimation at gate level where we have netlist consisting of standard cell, liberty files having power numbers of these standard cells, wire load model having information of interconnect capacitances, switching activity, clock tree information and operating conditions. At RTL level, some of the information especially the gate level netlist, clock tree information, placement, timing etc are missing.

For an RTL power estimation flow, we use a logic synthesis engine that could create a gate level model of the design in the same manner as actual synthesis would create in design cycle. This is because the power estimation tool does coarse synthesis and not the exhaustive that synthesis tool could do. Hence, further information as specified above needs to be provided to RTL power estimation tool so as to replicate actual synthesis environment for gate level flow.

For example, to estimate the clock tree power, we need some information from the synthesis engineer. We need to know which buffers will be used and what their fan-outs will be. This can be derived if we can get the number of flip flops per clock domain from the netlist, then we can calculate the number of buffers driving the flip flops, i.e. the number of flip flops divided by the fanout, would be the number of final clock buffers. We can then repeat the same process to get the rest of the clock tree. This would of course be not the most accurate method but this would help build the actual synthesis environment.

Accurate power estimation is crucial at the RTL level, so as to find the power-hungry segments and apply low-power architectures & techniques. Though the numbers at RTL are not as accurate as post-synthesis, the trends correlate for both.

About the authors
Aniruddha Gupta and Himani Grover contributed this article.

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