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Quick VRM design with perfectly flat output impedance

17 Aug 2015  | Steve Sandler

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Any discussion of power integrity includes a great deal of emphasis on the concept of target impedance and flat impedance requirements. But how do we design a voltage regulator module (VRM) specifically for flat impedance? This article will address not only that specific question, but how to accomplish it in five seconds or less.

I'm assuming that you haven't computed the required target impedance yet, since that's the tough part of this design problem. If you already know the design target impedance, you're in luck as you fall into the ".....or less" category and can go directly to step 2. I know you're sceptical, but since this is only a 5 second design, I'm hoping you'll bear with me to see that I'm serious. While it will take some time to explain the process, at the end I'll show you how to complete the process in less than 5 seconds.

The use of a current mode or current mode emulation topology significantly eases the design process, while also reducing the control loop complexity. While there are many devices to choose from, this particular article uses the Texas Instrument LM25116 as an example, since I have the evaluation board here and also because this particular evaluation board requires minimal modifications to achieve the desired flat impedance. The LM25116 is an emulated peak current mode controller, which also includes the required slope compensation and current waveform slope. These are set using a single, easily calculated capacitor.

This design process only requires a simple 2-port impedance measurement to verify the impedance flatness, though several other simple measurements are strongly suggested. The final design is easily "tweaked" using chip components to fine tune the impedance once it is constructed and why this fine tuning is necessary is also discussed.

Determining the target impedance
Assuming you know the voltage and current requirements of the VRM, the typical target impedance calculation is used to establish the output impedance of the VRM.

Using a 12Vinput 3.3V/10A output VRM requirement as an example, the target impedance is calculated as:

This is the MAXIMUM allowable impedance. In order to allow for component tolerances and to provide sufficient margin for switching ripple and dynamic load demands, the design target impedance is typically set much lower. A worst-case analysis assures the maximum is not exceeded. In this example, the nominal design target impedance is set to 14mΩ, determined, in part, to minimise the modifications to the evaluation board, which are somewhat difficult.

The most crucial step
We're most of the way through our VRM design now, with a single calculation needed to determine the fundamental VRM characteristic, transconductance. The current mode converter is the simplest to implement, since it can be represented as a transconductance block. The VRM output impedance is directly related to the transconductance (Gfs) by the relationship:

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