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Ensure closure with the right latch constraints

23 Sep 2015  | Babul Anunay, Syed Shakir Iqbal, Gourav Kapoor, Mitul Soni

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Latch exception handling

Figure 10: Latch setup and borrow check.

Figure 10 shows the two different interpretations of the setup checks present in latches. While the borrow check is from the start of the transparent or active level , the setup check is from the end of the active/transparent level backward just like it is present in an edge-triggered register. It is important to note that the EDA tool considers both for report timing i.e. based on reporting –edge_to lead or –edge_to trail of capture clock, it can show the same path in different manners. However, in most of the EDA tools for exception handling, only the register-type setup check from end of active/transparent edge is considered. Disabling it will nullify both the setup and borrow checks to the latch. For example, in figure 10,

set_false_path –rise_to {capture clock} does not show any impact

set_false_path –fall_to {capture clock} masks both time borrow and setup checks

This is very handy in places where latch based exceptions are common such as when exceptions are required to be applied on a particular polarity of latches used as lockup elements e.g., in a shift-atspeed capture-shift mode during testing. Thus to mask the setup timing to a negative level sensitive latch, the correct exception to make an EDA tool understand this would be:

set_false_path -setup -through {lockup_data_pins} -rise_to {all_clocks}

-rise_to ensures that the setup check (and the borrow check) to such all negative level sensitive latches are disabled.

In this way exceptions based on latches, whose usage is gradually increasing in the designs for the reasons discussed in this paper, can be accurately modelled to ensure a smooth and hassle-free timing closure of the design in various functional and testing modes as required.

About the authors
Gourav Kapoor is working as Senior Design Engineer at Freescale since June 2011, and currently working in physical design team. He has experience in synthesis and Static timing analysis.

Shakir Iqbal is a design engineer at Freescale Semiconductors India. He has worked with Freescale's automotive MCU division since 2012&is a part of the physical design team. He has been involved in constraint development&design timing closure for various SoCs at 65nm, 45nm and 28nm.

Babul Anunay completed his B.Tech in ECE from S.O.E. , Cochin University of Science & Technology, Kochi in 2010. He completed his M.Tech in VLSI Design & Embedded System from Delhi College of Engineering (now called Delhi Technological University) in the year 2012. He joined Freescale Semiconductors in the same year and has been working successfully as a Design Engineer in STA Domain of Physical Design since.

Mitul Soni also contributed to this article.

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