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Synopsys prototyping systems deliver 100MHz performance

18 Sep 2015

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Synopsys introduced the HAPS-80 FPGA-based prototyping systems and ProtoCompiler design automation and debug software. The HAPS-80 systems feature high-speed time-domain multiplexing (HSTDM) capacity and deliver up to 100MHz multi-FPGA (field programmable gate array). HAPS-80 with the ProtoCompiler software uses the latest Xilinx Virtex UltraScale VU440 devices with 26-million-ASIC-gates capacity/FPGA. The combination speeds up software development, system validation and hardware/software integration.

With built-in knowledge of the HAPS system, the ProtoCompiler software automates partitioning, enables an average time to first prototype of less than two weeks, and subsequent compile iterations in hours compared to non-integrated prototypes. The software takes advantage of HAPS-80's HSTDM capabilities to automatically select the optimum mix of pin-multiplexing schemes to best match the design under test. The integrated HAPS-80 solution delivers performance of up to 300MHz for single FPGA designs, up to 100MHz for multi-FPGA without pin-multiplexing and up to 30MHz for multi-FPGA with high-speed pin-multiplexing. The increased system performance of the HAPS-80 systems enables OS booting to the command prompt in less than a minute, allowing designers to probe and initialise device hardware such as CPU, timers and UARTs. HAPS-80 also enables at-speed operation of real world I/O.

ProtoCompiler's automated RTL-to-FPGA image timing-driven flow delivers higher prototype performance and quicker turnaround times compared to the previous generation. The software enables the creation of prototypes with multi-FPGA design partition, low pin multiplexing ratios, synthesis, and guided FPGA place and route. These features enable designers to utilise the entire capacity range of HAPS-80, which supports up to 1.6 billion ASIC gates. ProtoCompiler's hierarchical IP-to-SoC flow encapsulates RTL, design prototyping constraints, pre-defined debug visibility access points and synthesis directives, eliminating the need to replicate these tasks in an SoC (system on chip), and reducing the integration time by weeks.

HAPS-80 systems deliver debug visibility and automation through always available HAPS Deep Trace Debug Gen4 (DTD4) technology, providing the ability to capture more than 1000 debug signal bits/FPGA at speed. Debug data acquisition, debug storage memory and dedicated debug routes are built into the HAPS-80 systems and automatically inserted by ProtoCompiler to ensure minimally invasive debug is always available to the user. HAPS DTD4, in combination with Synopsys Verdi debug software, helps designers rapidly visualise complex design behaviour in the context of the original RTL source for a simulator-like experience, reducing debug time by up to 50 per cent. In addition, the integration of HAPS and ProtoCompiler with the Verification Continuum's Unified Compile technology eases migration between Synopsys VCS simulation, ZeB emulation and HAPS prototyping to save up to months of design and verification time.

The HAPS Universal Multi-Resource Bus (UMRBus) host connectivity enables hybrid prototyping, global accessibility and prototyping farm use modes. The UMRBus provides seamless connection between HAPS-80 systems and Synopsys' virtualiser-based virtual prototypes to create an integrated hybrid prototyping environment for early software development and hardware/software integration. In addition, HAPS-80 is backward compatible with HAPS-70, enabling designers to reuse existing systems and hardware accessories. The native Ethernet connection in the HAPS-80 system enables global system accessibility via standard Ethernet. The HAPS-80 solution supports multi-design mode to execute multiple designs simultaneously across HAPS systems in an enterprise configuration, delivering the highest prototype utilisation and a greater return on investment for multiple project usage.

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