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Knowing the aspects of IC power dissipation

06 Oct 2015  | Sunil Deep Maheshwari, Naveen Srivastava, Rohit Ranjan

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Sometimes, those involved in IC design can get quite a limited view of their particular speciality area. This article, while covering some basics, aims to provide a global overview to everyone on the team, with a focus on power use (and reduction in a forthcoming article). With the reduction in size of MOS, the world of chip manufacturing has become susceptible to quantum effects which can play havoc with power consumption.

Power consumption in a chip
The power consumption in a chip can be divided into three major categories. These are: Dynamic Power, Short Circuit Dissipation, and Leakage Power Dissipation. Each of these categories and their components are discussed below in detail. Please note that unless otherwise mentioned, the description below refers to NMOS only – similar explanations can be derived for PMOS as well. "MOS" is used to refer to MOSFET and CMOS in general.

Leakage power dissipation
This component of power dissipation is getting the most attention these days. Not all the components of leakage consumption existed or dominated for quarter micron and above nodes and thus, it contributed a negligible portion of the overall power consumption. However, with the shrinking of MOS due to technology advancements, the quantum mechanical effects started coming into picture and resulted into many of these leakage current components. This is the component of energy dissipation which affects operation of chip largely in the standby operation as other components seize to play during that period. Therefore, to achieve low power target in a chip, one has to look for various sources of leakage components which might come into play. Major sources of leakage consumption are as below:

a. Weak Inversion Current/Sub-threshold Current: Sub-threshold region of MOS is the region of operation where VGS≈VT and VDS>0 (in the context of an nMOS). In this region, the voltages are not sufficient to build a complete surface channel for MOS to start conducting. However, some of the electrons may gain enough energy to cross over from source to drain. This current is called sub-threshold current. The approximate value of this current can be understood from the equation below:


iSUB = Sub-threshold current

α = Some process and technology dependent constant.

T = Temperature in Kelvin

Cox = Capacitance due to oxide.

n = another process dependent constant.

VGS = Gate-source voltage

k = Boltzmann constant

VT = Threshold voltage

W = Channel width

L = Channel Length

q = Charge on an electron

As we can see from above equation, the sub-threshold current increases with decrease in L, increases exponentially with drop in VT and increases with temperature. As the CMOS process shrinks, L decreases and VT has to be decreased for better functioning of the MOS logic (higher VT devices require more time to switch their state, which reduces the maximum operation speed of the device). Therefore, this current increases with the lowering of the technology nodes and become substantial at deep-subµm technologies. When the circuit operates in proper saturation/off region, this region of operation does not come into play. However, during low power operation when the voltage is reduced, one may reach a stage which satisfies the voltage conditions conducive for sub-threshold region of operation and this component becomes substantial. Also, one should note that the analogue circuits use this range of operation quite abundantly for their circuit implementation to use high gain region in this range of operation.

Figure 1: Various Leakage Currents.

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