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Design techniques to minimise IC power consumption

07 Oct 2015  | Sunil Deep Maheshwari, Naveen Srivastava, Rohit Ranjan

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Power Gating: There can be applications where certain blocks of the chip might not be required to function in some of the low power modes like sleep, deep-sleep, standby mode, etc. and only a part of the device is required to function. In such cases, it makes sense to power off non-functional blocks so that device does not have to power unused blocks. This not only helps reduce the dynamic consumption but leakage power is also saved for such a power gated block. However, while dealing with such a technique, design has to make sure that signals coming in from power-gated blocks do not affect the functioning blocks while operating in low power. For this purpose, isolation blocks are placed in the path so that functionality corruption does not take place, as can be seen in figure 2. Please note that the isolation signals are not required for signals going out of always-ON domain to other power domains as they are never supposed to go non-deterministic.

Figure 2: Power Gating.

Process based power reduction techniques
There are a lot of components of power consumption and not all can be targeted using Architectural Techniques alone. Power consumption due to effects like Drain Induced Barrier Lowering, Gate Induced Drain Leakage, sub-threshold leakage, etc. can be controlled most effectively using process based techniques. Below are some of the most commonly employed Process Based Techniques:

Multi Threshold Voltage CMOS Cells: A lot of MOS characteristics are governed by the threshold voltage of the cell. Sub-threshold current is the current between source and drain when the gate voltage is below threshold voltage. Mathematical expression for approximate value of this current is :

As one can see, this current reduces when threshold voltage VT is increased. Therefore, higher VT cells can be placed to decrease this component. However, as we have seen in propagation delay above, increasing VT has a negative impact on frequency of operation. Therefore, designers have to adopt a strategy to mix lower VT and higher VT cells in a way to reduce the leakage current while maintaining the desired frequency of operation. To implement this strategy, high VT cells are used as sleep transistors which gate the supply to further low VT based design when the block is supposed to be in standby mode. When device is in active mode, these sleep transistors are turned ON, and low-VT blocks downstream of this sleep-transistor can get the power and work as usual. This helps in reducing the current in standby mode. Alternatively, various data paths are categorised in terms of timing critical versus non-timing-critical paths. Timing critical paths can be implemented with cells of lower VT (known as LVT (lower VT) cells) so that the same operation can be achieved in less amount of time as compared to a path implemented with high VT cells (also abbreviated as HVT cells). This mixed usage approach balances the leakage current even when the chip is in run mode.

Another solution is to dynamically change the VT of the cells as per the application requirement. This can be achieved by varying the well/body biasing voltage using a control circuit. This requires more complex MOS fabrication as it requires twin-well or triple-well fabrication technique. This is more commonly known as Variable Threshold CMOS (VTCMOS). However, one should note that lowering the VT also compromises with the reliability of the chip as even lower voltage swings can cause the logic to start functioning in an incorrect fashion. These voltage swings can arise due to various process or environmental variations. Therefore, one has to be very cautious while decreasing the VT of the cells so as not to compromise on the sanctity of the final application.

Mutli VDD Technique: As we can see from the equation above, there is a quadratic relationship between device voltage VDD and dynamic power consumption. Therefore, one can reduce the dynamic voltage substantially by reducing the supply voltage. However, voltage reduction has its downside as well. Propagation delay of a cell is as below :

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