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Design techniques to minimise IC power consumption

07 Oct 2015  | Sunil Deep Maheshwari, Naveen Srivastava, Rohit Ranjan

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As one can see from equation above, reduction in the VDD increases the delay of the cell. As a result, the operating frequency of the cell reduces when one reduces the supply voltage. Therefore, one has to maintain a balance between voltage supply and associated performance.

Figure 3: Voltage Islands – Multi VDD Operation.

A solution to this challenge can be to create voltage islands in the design where low performance slow peripherals can be powered using lower supply voltage and performance critical blocks can be powered using higher voltage. However, design has to make sure that appropriate voltage level shifters are placed on those signals which talk across the voltage domains.

This technique also reduces Gate Induced Drain Leakage effect and associated power consumption in a device.

Dynamic Voltage and Frequency Scaling: Voltage Island technique, also known as Static Voltage Scaling presents few constraints while operating the device. This technique is not adaptive to the application needs and voltage supply to a block cannot be changed once designed. However, Dynamic Voltage Scaling technique liberates designer and customer of such limitations. This technique makes use of a regulator which can be programmed to deliver voltage levels as required. Therefore, various blocks can get configurable voltage and the customer/user can change the voltage settings as per the application settings. This can help save the power dynamically. Various solutions have also been used where the design freed the software to make changes to voltage scaling. The design itself senses the current-load requirement in the device and makes the voltage adjustments accordingly. This technique helps reduce power consumption in a more adaptive manner.

The same voltage scaling can also be clubbed with dynamic frequency scaling where the frequency of a block can be changed by the software as needed. Therefore, a block running on lower VDD can be clocked by a slower clock while maintaining the performance and functional requirements. This technique helps reduce dynamic as well as leakage power consumption in the device.

Figure 4: Differential Voltage and Frequency Scaling.

Fully Depleted Silicon on Insulator (FDSOI): This is another technique which helps reduce various components of leakage currents which are more of a menace at lower technology nodes. Leakage components like GIDL, Reverse bias current and Gate tunnelling currents can be controlled very effectively using this technique. In this technique, the MOS sits over an ultra thin film of oxide which insulates the cell from rest of the body. On top of this oxide film, a very thin layer of silicon is deposited which acts as a channel. Due to its thinness, channel can be established in this layer without any additional doping of the same. For this reason, it is known as fully depleted SOI.

Figure 5: FDSOI Cell (Left) and Various Leakage Currents in CMOS Cell (Right).

In another technique a small neutral region is deposited in the depletion region under gate. Here, channel thickness need not be as thin as required in FDSOI. This is known as partially depleted SOI (PDSOI). However, PDSOI tends to have higher VT (and therefore slower operation) and larger gate-effects as compared to FDSOI (hence, larger leakage currents). Therefore, due to better control over VT and drastically reduced leakage currents, FDSOI is a preferred choice for small process nodes (usually below 90nm).

The article discussed various solutions which can be adopted to achieve target current requirements. However, all of these have pros and cons. Therefore, designers often mix various solutions to reach the optimum level which meets not only current requirements but also takes care of performance and cost of the device to make the product sellable.

About the author
Sunil Deep Maheshwari, Naveen Srivastava and Rohit Ranjan contributed this article.

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