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Reusing UVM RTL tests for gate level simulation

13 Oct 2015  | David Vincenzoni

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When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analogue blocks as well, we want to check all the implemented features and possible corner cases to minimise verification time. A mix of several techniques and methodologies are used to improve the functional verification and extract a measure of the grade of coverage: Formal verification and random constrained tests based on Universal Verification Methodology (UVM) increase the probability to discover bugs. Sometimes we create a perfect and effective test for RTL verification only to find out it can't be reused during the gate level simulation because the UVM Monitors are hooked on internal SoC signals that can disappear or change after the implementation phase.

This article will describe how easy it is to create efficient self-checking tests that are straightforward, and reusable during gate level simulations. It is surprising that, by changing the data flow, we can have benefits for the test bench, reducing the complexity of scoreboards, which also means less time for test developing.

The flow is based on the instantiation of UVM Verification Components used for checking interfaces such as SPI, I2C, & UART, but it can also be extended for more complex interfaces.

SoC verification flow
The most effective SoC verification is based on the instantiation of several UVM Verification Components (UVM VC) placed inside the internal buses, on specific internal modules, and on the primary SoC interfaces. These UVM VC are used as bus protocol checkers (e.g., AMBA checker); serial protocol checkers, and active masters (e.g., I2C, SPI, UART, JTAG, SATA, PCIe).

The tests developed based on UVM should be self-checking; every action, stimulus and transaction, must be verified by a checker, which in case of a mismatch raises a "flag" that stops the simulation and issues an error message that is shown on simulator console and written into a log file.

The verification of communication interfaces (e.g., SPI) needs the use of UVM VC formed by a Collector that gets its transaction on bus, a Monitor that checks the compliancy of protocol, and a Bus Functional Model (BFM) that generates the transactions. The data exchanged between the SoC and external UVM VC are verified through a module named scoreboard.

This scoreboard has at least two ports where the added object is matched with a second one – the reference. In case of a mismatch, an error is issued. This kind of checker must be reused during the gate level simulation in order to stimulate the critical paths. Figure 1 shows a simple block diagram of a verification test bench that uses several checkers for an effective verification methodology.

Figure 1: Typical UVM Verification Test Bench.

The yellow blocks are UVM VC. The Bus Monitor is a passive component that has only the monitor and checker.

A common data flow, for testing a serial peripheral, is to send data from the UVM VC towards the microprocessor and check that the data have arrived at the destination (microprocessor). In the second step, we send data from the microprocessor to the UVM VC checking that the correct data have arrived to the destination (UVM VC).

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