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Capacitance meter utilises PLL for high accuracy

12 Oct 2015  | Jim McLucas

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The circuit applies the 6FO signal, divided by three, to buffer IC5F's Pin 5. This action provides an output frequency whose period is proportional to the value of the measured capacitance. The output provides the correct digits without regard to the location of the decimal point. To determine the value of the unknown capacitance, observe the setting of S1 and S2.

You can calibrate the circuit by using a capacitance of a known value of approximately 1000 pF, with S2 at the low-capacitance position and S1 at the 100- to 1000-pF/0.1- to 1-µF position. Set R22 at its midposition, connect a frequency counter to Pin 6 of IC5F, and set the meter to measure the period of the signal. Adjust R12 for a period whose digits agree with the known value of capacitance. Next, use a capacitance of approximately 100 pF and set S1 to the 10- to 100-pF/0.01- to 0.1-µF position. Record the measured value of the capacitor. Then, using the same capacitance of approximately 100 pF, set S1 to the 100- to 1000-pF/0.1- to 1-µF position and adjust R22 to get the same value as you obtained on the 10- to 100-pF/ 0.01- to 0.1-µF position. The R22/C13 combination provides a small variable delay relative to the signal at Pin 14 of IC3. This fine adjustment improves accuracy in the lower range.

Employing measurements made with the available equipment, which did not include an accurate, high-resolution capacitance meter, this meter is accurate to approximately ±2% over 100 pF to 10µF (table). The accuracy degrades over 10 to 100 pF because of the input capacitance of the op amp and the associated parasitic capacitance at IC1's Pin 3. R7 and C6 provide some compensation at the 10- to 100-pF range for the inherent capacitance at that node. R5 and C5 provide compensation at the 1- to 10-pF range.

Table: Capacitance measurements.

You can also measure the inherent capacitance and then subtract it from the reading on the two lower ranges. If you take this approach, omit R5, R7, C5, and C6 from the circuit. Then, with S1 at the 1- to 10-pF range and S2 at the low-capacitance position, you can measure the capacitance at that node with no external capacitance. The intrinsic capacitance of the test circuit is 2.8 pF. Using this correction, the values you obtain on the lowest two ranges are accurate to approximately ±2%, or ±1 pF.

You must observe capacitor polarity when measuring electrolytic capacitors. Connect the negative end of the capacitor to the grounded terminal. Also, the circuit provides no overvoltage or ESD (electrostatic-discharge) protection, so be sure to discharge the capacitors before connecting them to the capacitance meter and use an ESD wrist strap to avoid damaging the circuit. For best results, you need accurate and stable 5 and 8V power supplies. Both supplies should be accurate to ±2%. You can raise the 8V supply to 9V and relax the accuracy to 5%. If you use a 9V battery to supply the 8V, you can let the voltage drop to about 7.9V before adversely affecting the performance of the meter. You must, however, maintain the 5V supply at a constant, accurate value. Note that all of the ICs except IC1 have 0.1-µF bypass capacitors from their 5V pins to ground.

Pyle, Ronald E, "Phase-locked loop aids in measuring capacitance," Electronics Designer's Casebook, No. 4, pg 32.

About the author
Jim McLucas is from Broomfield, Colorado, United States.

This article is a Design Idea selected for re-publication by the editors. It was first published on October 8, 2009 in

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