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Active voltage positioning minimises output capacitors

19 Oct 2015  | Robert Sheehan

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Power supply performance, especially transient response, is crucial in meeting today's demands for low voltage, high current microprocessor power. In an effort to minimise the voltage deviation during a load step, a technique that has recently been named "active voltage positioning" is generating substantial interest and gaining popularity in the portable computer market. The benefits include lower peak-to-peak output voltage deviation for a given load step, without having to increase the output filter capacitance. Alternatively, the output filter capacitance can be reduced while maintaining the same peak-to-peak transient response.

Basic principle
The term "active voltage positioning" (AVP) refers to setting the power supply output voltage at a point that is dependent on the load current. At minimum load, the output voltage is set to a slightly higher than nominal level. At full load, the output voltage is set to a slightly lower than nominal level. Effectively, the DC load regulation is degraded, but the load transient voltage deviation will be significantly improved. This is not a new idea, and it has been observed and described in many articles. What is new is the application of this principle to solve the problem of transient response for microprocessor power. Let's look at some numbers to see how this works.

Figure 1: Transient Response with Load Step from 0A to 12A.

Assume a nominal 1.5V output capable of delivering 15A to the load, with a ±6% (±90mV) transient window. For the first case, consider a classic converter with perfect DC regulation. Use a 10A load step with a slew rate of 100A/µs. The initial voltage spike will be determined solely by the output capacitor's equivalent series resistance (ESR) and inductance (ESL). A bank of eight 470µF, 30mW, 3nH tantalum capacitors will have an ESR = 3.75mW and an ESL = 375pH. The initial voltage droop will be (3.75mW • 10A) + (375pH • 100A/µs) = 75mV. This leaves a 1% margin for set point accuracy. The voltage excursion will be seen in both directions, for the full load to minimum load transient and for the minimum load to full load transient. The resulting deviation is 2 • 75mV = 150mV peak-to-peak (figure 2a).

Figure 2: Transient Response Comparison.

The transient with active voltage positioning
Now look at the same transient using active voltage positioning. At the minimum load, purposefully set the output 3% (45mV) high. At full load, the output voltage will be set 3% low. During the minimum load to full load transient, the output voltage starts 45mV high, drops 75mV initially, and then settles to 45mV below nominal. For the full load to minimum load transient, the output voltage starts 45mV low, rises 75mV to 35mV above nominal, and settles to 45mV above nominal. The resulting deviation is now only 2 • 45mV = 90mV peak-to-peak (figure 2b). Now reduce the number of output capacitors from eight to six. The ESR = 5mW and ESL = 500pH. The transient voltage step is now (5mW • 10A) + (500pH • 100A/µs) = 100mV. With the 45mV offset, the resultant change is ±55mV around centre, or 110mV peak-to-peak (figure 2c). The initial specification has been easily met with a 25% reduction in output capacitors.

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