Path: EDN Asia >> Design Centre >> IC/Board/Systems Design >> How to reduce digital IP design time
IC/Board/Systems Design Share print

How to reduce digital IP design time

27 Nov 2015  | David Vincenzoni

Share this page with your friends

The number of available APPs is growing very fast, and this will permit a move of verification tasks from dynamic to static, improving the coverage and reducing verification time. Of course, the Formal flow has some limitations and currently cannot be used to verify everything; when the number of states to be analysed (that is the 'Formal complexity index') is too large, the engines are not able to converge and analyse the code exhaustively. This is a challenge that can be surmounted in the near future through the introduction of new algorithms and computational power. Anyway, we cannot claim that the Formal flow will surpass dynamic simulation for a simple reason: the use of 'assume' statements introduce the risk of hidden bugs, and if the property succeeds, it could be possible that RTL behaviour will be wrong in case the assume conditions are not met in the real application. This is totally analogous to the Static Timing Analysis (STA) and Gate level simulations: if the timing constraints are wrong, the STA says that no timing violations are in the design, but at the end the design will not work on some corner case. Dynamic simulations allow us to validate the Formal 'assume' statements as well as the STA constraints.

For these reasons, the next step of verification flow needs to be UVM simulation, boosted by the property assertions that are succeeded in the Formal steps and are now re-used in the dynamic simulations as well. The number of tests developed in this new flow will be less than those developed using the flow illustrated in figure 1, because we can focus on the part uncovered by the Formal flow and develop limited tests for the part analysed with it.

The last steps of the flow shown in figure 2 are basically the same: we run the unreachability analysis in order to remove the unreachable code, and then we analyse the code and functional coverage.

The use of the Formal Verification approach as the first step of the flow represents a different methodology that better exploits the benefit and effectiveness of the Formal: zero time is spent to build the test bench and exhaustive verification of the RTL. Moreover, the learning curve for using this methodology is faster than UVM; the language used for writing the assertions is compact (either PSL or SVA) and easy to use. The most difficult job is the definition by human language of the correct properties that best describe the functionalities that we want to prove. The translation into SVA or PSL becomes easy work.

The main advantage of using the Formal methodology in the early stage of RTL verification is to enter dynamic simulation with cleaner code, where many features have already been exhaustively verified and some bugs fixed. Since the Formal methodology permits us to shrink the time spent on the verification of features, it results in a drastic reduction of overall verification time.

We used this new flow for the verification of IP (with AMBA interfaces for configuration and data exchange), and experienced a reduction of over 30% in the time spent verifying the RTL code.

About the author
David Vincenzoni graduated in Electronic Engineering, majoring in Telecommunications, in 1996 at Perugia University. He worked for the biggest Italian Telecommunication Company in the R&D lab working on algorithms for Digital Signal Processing and their implementation with custom circuits. Then, in 2000, he moved to a design services company, working as Project Leader. During these years he worked on several SoCs based on ARM architectures and Digital IP design and verification. From March 2007 he has been working at STMicroelectronics as Project Leader and then R&D Design Manager responsible for the design and verification of new chips for Broadband Power Line Modems and for the new families of devices for Industrial application.

 First Page Previous Page 1 • 2 • 3

Want to more of this to be delivered to you for FREE?

Subscribe to EDN Asia alerts and receive the latest design ideas and product news in your inbox.

Got to make sure you're not a robot. Please enter the code displayed on the right.

Time to activate your subscription - it's easy!

We have sent an activate request to your registerd e-email. Simply click on the link to activate your subscription.

We're doing this to protect your privacy and ensure you successfully receive your e-mail alerts.

Add New Comment
Visitor (To avoid code verification, simply login or register with us. It is fast and free!)
*Verify code:
Tech Impact

Regional Roundup
Control this smart glass with the blink of an eye
K-Glass 2 detects users' eye movements to point the cursor to recognise computer icons or objects in the Internet, and uses winks for commands. The researchers call this interface the "i-Mouse."

GlobalFoundries extends grants to Singapore students
ARM, Tencent Games team up to improve mobile gaming

News | Products | Design Features | Regional Roundup | Tech Impact