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Guide to analogue IP verification

25 Nov 2015  | Stefano Pietri

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Exceptions to these guidelines should be always be documented, reviewed and signed off by global team of experts and your manager.

2. Simulations required for IP verification
Running thousands of simulations may require many years for some IP's

 • If this is the case, there are block-specific simulation techniques that can be run instead that take less time and still provide sufficient evidence that the circuit is robust and production ready:
 • Use of VerilogA or mathematical models
 • Reduced scope simulations
 • Fast simulators
 • Sub-blocks would still require full verification following the guidelines described in this document
 • Review your ideas with your senior designers and experts so they can help you in setting up a comprehensive verification plan even with a small number of circuit simulations.

4-sigma corner analysis Each design should pass 4x standard deviation corners, shortly 4-sigma corners at full V/T conditions.
 • In our experience most silicon/simulation differences would be replicated with 4-sigma corners, and in some of these cases typical silicon would be aligned with 4-sigma corners.
 • Use good judgement and discuss with Sr. designers
 • If one extreme corner is marginally failing, it might be possible to disregard it by collecting enough data in Monte Carlo simulations to show the circuit has good CPKs.
 • If meeting corners requires additional cost (like 2x area or 2x power), analysis might be reduced to 3-sigma corners. There are cases where a little yield loss (0.1% or less) can be preferable to a 2x area/power increase.
 • Expert design team and modelling group should set up a thoughtful 4-sigma corner set for each technology that includes variations of all devices in the technology, including FETs at different oxide thicknesses, BJTs, diodes, resistors, capacitors, and inductors.

Monte Carlo simulation of at least 1000 samples per V/TUse local and global variations for all technology devices.
 • Other variables should be defined as statistical when possible (normal or uniform distribution).
 • Objective is to prove the CPK has been met:
 • Automotive quality: each parameter must meet CPK >= 2.
 • Use good judgement and discuss with Sr. designers. If a CPK=2 requires 2x area or 2x power, a CPK> 1.67 may be acceptable for a few parameters, when a small yield loss is preferable to large area/power increase
 • For power consumption/leakage, CPK > 1.3 is acceptable
 • Monte Carlo simulation can be run at sub-block level for complex IPs, given that 6-sigma parameter limits will be used for top level IP simulation.
 • At top level a smaller number of simulations can be used to prove equivalent results between sub-block and top.
 • Fast Monte Carlo simulators have been proven to be effective with small sample sizes and still correctly evaluate the design at large sigmas. You may use them to your best advantage if available.

Side by side comparison to prove that extracted layout and schematic agreeFor technologies of 40nm and beyond, layout dependent effects (WPE, LOD...) can largely skew simulation results, even the DC point of your circuit. Early assessment of post-layout simulation helps reduce design effort.
 • A subset of corner simulations or reduced Monte Carlo is acceptable because an RC-extracted netlist is long to simulate.
 • When RC extraction is not feasible, R-only and C-only extractions are allowed.
 • R-only preferred for DC-accurate circuits like PMC
 • C-only preferred for dynamic circuits like ADC or charge pump
 • The comparison between schematic and extracted is preferably achieved with a single simulation setup that runs the two side by side and reports results side by side.

Run reliability and stress simulations on top level schematic with typical voltage
Typical process, voltage and temperature corners are to be considered. Reliability is mostly a statistical forecast based on interpolation.

Verify that all reliability/stress violations are reviewed together with a reliability expert.

Run EM verification, check your power grid
Silicon Frontline or an equivalent tool must be used to check there are no bottlenecks in the supply/ground grid.
 • Electromigration must be checked under worst case high voltage/high temperature conditions, where transistors and metals are more susceptible.

Run ageing on top-level schematic under extreme corners Verify that degradation does not skew parameters beyond acceptable limits.
 • Ageing simulation can be run preferably with ageing model back-annotation that takes into consideration differential ageing of matched transistors.
 • Ageing would be run only on mature IP with stable PDK.
 • All final simulation results must be stored in a repository, and tagged together with the version of the IP.

3. Recommendations for power management simulations Understand your load.
 • Series resistance of routing tracks may change phase margin significantly.
 • External caps have a roll off not predicted by simple ESR.
 • External ballast beta will vary ±35% over corners.
 • Transient load is different for each technology and each package.
 • Package RLC effects can be predominant over external capacitor ESR.

Most of the defects in power management are related to start-up:

 • Start-up helpers are in band-gaps, current references, oscillators, etc.
 • Simulate transient slow and fast ramp rate, high and low supply across PVT, and mismatch (which is really important).
 • Start-up circuits must engage and disengage correctly.
 • A broken start-up may cause the entire device to malfunction: simulate your start-up in an attempt to break it, not to make it work.
 • Use soft start circuits for all your regulators, unless you can tolerate large overshoots, difficult to replicate without all board parasitics.

OP/DC simulation to verify offset
AC simulation to verify stability

 • MATLAB (and similar free tools) & Verilog models can be used to study stability of linearized switched systems (DC-DC)
 • Keep your phase margin > 35 degrees
 • AC analysis is not reliable without transient analysis; both must be run.

Transient simulation to verify transient behaviour Small step response analysis
 • Large signal analysis with realistic maximum peak/peak step input
 • Load/line regulation
 • Overshoot/undershoot
 • Noise, PSRR, etc.

Note by the author: This document is a living entity and collects the thoughts of expert global designers, including J. Kruecken, H. Bode, A. Laudenbach (Munich team), B. Braswell, D. Garritt, P. Hickman, S. Allen (Phoenix team), C. Verma and J. Banerjee (Noida team), J. Alvarez, S. Herrin, C. Dao, J. Ren, A. Kumar (Austin team). I would like to thank everyone who collaborated on these guidelines for their time and effort.

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