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Thermal analysis of small outline packages

08 Dec 2015  | Robert Day, Prasad Tota

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Several parameters effect the thermal conductivity of the board in the region of the vias.[4] Creating a test board for every possible thermal via configuration and testing in a lab is practically infeasible. The CFD tool can be used to perform sensitivity studies of thermal performance to various via parameters, such as the pitch, plating thickness, and fill material (figure 6). Such computational studies reduce the number of prototypes needed for testing or validation.

In a CFD program, it is computationally intensive to model each and every via discretely, so we took a lumped approach where we replaced the region of vias with a block of orthotropic conductivity that had in-plane conductivity (kxy) and through-plane conductivity (kz). A board-import tool in the software was used to calculate the kxy and kz of this via block, but we could also have calculated these values analytically.[2, 5]

Thermal vias with an outer diameter of 0.3 mm were studied. Figure 7 shows the sensitivity of thermal conductivity of via block to pitch and plating thickness (t). The dielectric material used in this calculation was FR4 (k = 0.3 W/mK), and the fill material was pure copper (k = 385 W/mK).

Figure 7: Sensitivity to via pitch and plating thickness. kz: in-plane conductivity.

Thermal simulations were conducted for PSOP in still air based on the conductivity values of the via cuboid, and results are shown in figure 8. The results show that when plating thickness t is 75µm or higher, even sparsely populated vias are sufficient. However, at low plating thickness, say 25µm or lower, the vias need to be populated densely to ensure the component does not experience thermal failure.

Figure 8: Junction-to-ambient thermal resistance (?ja) to via pitch and plating thickness in still air.

Validating the simulation results
We conducted lab experiments to validate the CFD model results. The IC inside the PSOP package is capable of dissipating 10 Watts of power and has an integrated temperature monitor. The relationship of the voltage at monitor-to-die temperature is not an absolute temperature indicator. However, the change in voltage verses temperature is a reliable indicator of relative changes in die temperature. Calibrating the temperature-monitor voltage verses temperature function was the first step in understanding die temperature used to determine thermal resistance.

The PCB we used in the lab was FR4-grade with six layers of copper and exposed copper planes, onto which the ADA4870-1 PSOP package was soldered and heatsinks were mounted. We used copper-filled thermal vias to conduct heat from the IC side to the bottom of the board where a precise temperature sensor was soldered directly below the thermal slug of the PSOP package onto the back side of the PCB. We bolted a heatsink to the back side that straddled the sensor using silicon grease as a thermal interface material between the heatsink and the PCB. We used commercially available heatsinks (table 6).

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