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CTO describes BrainChip's neural network architecture

18 Dec 2015  | Peter Clarke

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The CTO and interim CEO of BrainChip Inc. has unveiled more details of the company's spiking neural network architecture, SNAP64. Talking about the company's technology known as SNAP (standing for Spiking Neuron Adaptive Processor), Peter van der Made attempted a closer modelling of biological neural networks, including the spike train method of data transfer and modelling of multiple modulations of signals at the synaptic connection, which is one of the main differences between BrainChip's implementations and some other neuromorphic processors implemented in both hardware and software.

"The number of neurons and synapses is configurable in the RTL. We could put as many as 10,000 neurons and five million synapses on a single die. These are neurons that behave like biological neurons with multiple spiking modes and dynamic, temporal integrating synapses," said Van der Made. He added: "The neurons and synapses are not multiplexed, unlike other designs like IBM's TrueNorth, which are multiplexed 256x and do not learn."

Peter van der Made

van der Made: The number of neurons and synapses is configurable in the RTL.

"The advantage of not multiplexing is that they are thousands of times faster, that all memory can be distributed, which simplifies the learning method. The learning method we use is STDP, Spike Time Dependent Plasticity, which constantly accesses memory," said Van der Made.


The use of distributed memory located at the synapses means that SNAP64 is capable of updating neurons at a rate of millions per second and this has been taken up to 4Mupdates/s in an FPGA implementation, Van der Made said.

The circuit implementation of SNAP64 is all-digital although the spikes are spatially and temporally distributed and asynchronous. The SNAP64 RTL has been implanted on a FPGA board from Dini Group La Jolla Inc. with multiple 20 million gate Xilinx FPGAs.

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