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Leti unveils techniques to advance FDSOI

18 Dec 2015  | Peter Clarke

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CEA-Leti, a French research institute, developed two techniques to put local strain in the silicon channel of a fully-depleted silicon-on-insulator (FDSOI) manufacturing process.

STMicroelectronics and GlobalFoundries are championing the FDSOI process as a means to achieve world-class energy efficiency in leading edge integrated circuits without the complexity and expense of FinFET manufacturing.

Strain on the crystal lattice is used routinely to increase mobility in conventional planar CMOS and in FinFET CMOS. Leti is now proposing its use on next-generation FDSOI circuits to realise the same benefits: higher performance at the same or lower power consumption.

Two techniques are required because p-channel FETs in FDSOI require compressive strain of silicon-germanium channel material while a tensile strain is required to improve the silicon n-channel FET. The two techniques Leti has developed can induce local stress as high as 1.6GPa in the channel.

The first technique uses the transfer of strain from a relaxed SiGe on top of the SOI film. This has been used to boost short-channel electron mobility by more than 20 per cent.

The second technique relies on creep in the buried oxide under high temperature annealing to insert tensile strain in the overlying silicon. BOX-creep can also be used to introduce compressive strain, Leti said.

Such strained channels enable an increase in the on-state current of CMOS transistors and more performance at same power or a reduction in power consumption for a given performance. While stain was not necessary for 28nm FDSOI it is beyond the 22/20nm node, Leti said.

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