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How to simulate the front-end of ADC

29 Dec 2015  | Bonnie Baker

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The voltage reference pin, REF, requires a stable voltage to be present during the conversion process, or after the CONVST pin becomes a high value (figure 2). While CONVST is low, the converter is acquiring the input signal (acquisition mode). The SAR-ADC macro-model has a 1MHz clock and does produce the CONVST signal. The voltage reference pin must settle at the end of the bit conversion periods throughout the entire conversion time of the converter to a half LSB level.

Figure 2: In this three-wire timing diagram with three-wire operations, CONVST functions as chip select.

The TINA-TI model for the ADS8860 in figure 3 samples the input signals on AINP and AINN and presents the results on the model's AINPsmpl and AINMsmpl.

Figure 3: Here is a TINA-TI macro-model of a SAR-ADC.

In figure 4, the input at AINP is equal to 3V, and the reference voltage is equal to 4.096V. As you test the accuracy of the input signal, set the ADS8860 TINA-TI circuit to sense the difference between the output of the amplifier driver, AMP_OUT_sig, and its output signal, AINPsmpl. As you look at this difference, examine the region at the end of the acquisition time or just before the CONVST pin goes high. Verify that the signal is less than half a LSB.

Figure 4: This set-up is for the TINA-TI circuit to monitor the analogue and reference inputs.

Once you have examined the analogue input function for accuracy, examine the stability of the voltage reference pin. As you measure accuracy of the REF pin, measure the difference between the voltage reference output (VF1) and the THS4281 amplifier output (AMP_OUT_ref). Be sure to remove offset errors generated by the voltage reference (REF5040) and op amp (THS4281) with the value of VERR1. While doing this, examine the voltage level just prior to the current spikes using the iref1 current meter. Reference 1 provides good in-depth information for this simulation.

Simulation is a tricky thing when it comes to SAR-ADCs. Presently there is no complete converter model that accurately models the entire device. The resource you do have is an analogue SPICE file that models the analogue input pin stability. The good fortune of having this tool available is that you have a powerful utensil to address one of the most critical, difficult converter issues.

But, this is half the story. You have only simulated the analogue part of the ADC. Next month we will talk about simulating the digital input / output of your converter.

1. "Using SAR ADC TINA Models: Much ado about settling," Munikoti, Harsha, Precision Hub, Texas Instruments, December 12, 2014

2. ADS8860 datasheet.

About the author
Bonnie Baker is applications engineer for WEBENCH Design at Texas Instruments.

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