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Examining PCB traces

25 Jan 2016  | Pi Zhang, Karl Morant

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One of the frequently asked questions during printed circuit board (PCB) layout review meetings is, "Are 50Ω traces being used for the digital signals in this PCB layout?" Often the answer to this question is "yes". However when making decisions that balance cost, performance and manufacturability the correct answer can also be "no" or "not for all the digital signals." Alternative approaches can include focusing on the "controlled impedance" of PCB transmission lines and/or using other trace-impedance values.

Let us examine a layer-stack design and see how the PCB trace width affects layer count (cost) and trace impedance (performance). In figure 1, routing channels of the same width are shown on a signal layer for three PCB transmission lines: a 100Ω differential pair, a 50Ω and 60Ω single-ended.

Figure 1: Routing channels of the same width are shown on a signal layer for three PCB transmission lines for a 100Ω differential pair, a 50Ω and 60Ω single-ended.

The 100Ω differential-pair is usually determined prior to the single-ended and should be fitted in the routing channel (between the vias) without discontinuities because they are usually for higher speed digital signals. Once the trace width and spacing of the 100Ω differential-pair have been designed, the trace width for 50Ω or 60Ω single-ended on the same layer is usually determined accordingly. Changing the trace width alone for the single-ended traces will lead to different trace impedance. The trace routing yield per channel is:

Right: One 100Ω differential-pair with 4mil trace / 5.5mil space.

Middle: Two 60Ω traces for single-ended with 4mil trace / 4mil space.

Left: One 50Ω trace for single-ended with 6.5mil trace / 7.4mil space.

Note: This example assumes that the minimum trace width and spacing are 4mils.

In this case, the engineer needs to make trade-off decisions on using either 50Ω traces, which use up more PCB space and possibly more layers, or 60Ω traces which use up less PCB space and possibly less PCB layers.

Using IC reference designs
The reference designs and recommendations in the documents provided by IC manufacturers are often used as starting points for schematics and PCB layouts in board-level hardware designs.

The techniques adopted for designing high-speed digital interconnects in these documents were most likely re-used in the designs for specific end-products. For example the decision to use a memory interface without termination could have been determined due to the large operating margins of the memory in the reference schematic. However, for cost savings the design engineer may choose alternate devices with different I/O buffer characteristics from those used in the reference design. The engineer would then need to decide if the non-terminated memory interface should remain in the new design.

Reference designs are an essential part of making PCB design decisions. However it is important to have a deep understanding of the principles and limitations behind the techniques being applied in the reference designs. Only then can optimal design trade-off decisions be made.

PCB traces and PCB transmission lines (PCB TL)
When characterizing the PCB traces for digital signals in a PCB design, the followings should be taken into account:

 • Rise-time (tr )/fall-time of the digital driver, and slew-rate-control if any
 • Output impedance (Zo), and drive-strength-control of an output buffer if any
 • Flight-time in the PCB trace (tpcb)
 • Internal terminations for both driver and receiver
 • External terminations at both driver and receiver

Figure 1: PCB TL.

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