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Software-defined FPGA computing with QuickPlay

23 Mar 2016  | Stephane Monboisset

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Data-centre equipment manufacturers have always been eyeing the massive parallelism possible with FPGAs to achieve the processing performance and I/O bandwidth needed to keep pace with demand, within a highly efficient power budget. Traditionally however, implementing a hardware computing platform in an FPGA has been a complex challenge that has required designers to deal with some of the lowest levels of hardware implementation.

Although some recent FPGA-design methodologies incorporating High-Level Synthesis (HLS) tools and software programming languages such as OpenCL, C, and C++ have simplified the task, they have not eliminated the need for specialist FPGA-design expertise. There is a need for a high-level workflow that allows software engineers to use an FPGA as a software-defined computing platform without the pain of hardware design. To satisfy this need, such a workflow should be able to:

 • Create functional hardware from pure software code
 • Incorporate existing hardware IP blocks if needed
 • Infer and create all of the support hardware (interfaces, control, clocks, etc.)
 • Support the use of commercial, off-the-shelf boards and custom platforms
 • Eliminate hardware debug by ensuring generated hardware is correct by construction
 • Support debug of functional blocks using standard software debug tools only

Consider a software algorithm comprising two basic functions: data is processed into one function and then sent to another for further processing. From a software perspective, this implementation is as simple as a call to Function1() followed by a separate call to Function2(), using pointers to the location of the data to be processed.

Figure 1: Functions to be performed on data.

Implementing such an algorithm on an FPGA-based hardware platform without the right hardware abstraction tool flow would require the software developer to come up with a hardware design resembling that in figure 2 (where Kernel 1 and Kernel 2 are the respective hardware implementations of Function 1 and Function 2).

Figure 2: A detailed hardware implementation of a two-function algorithm using traditional FPGA tools.

The hardware design would need to include both the control plane and the data plane. The control plane is the execution engine that generates clocks and resets, manages system start-up, orchestrates data plane operations, and performs all housekeeping functions. The data plane instantiates and connects the processing elements, Kernel 1 and Kernel 2, as well as the necessary I/O interfaces required to read data in and write processed data out. In the example shown in Figure 2, those interfaces are Ethernet and PCI Express (PCIe).

Familiar challenges
A software developer without specific hardware expertise could generate Kernel 1 and Kernel 2, using a high-level synthesis tool such as Vivado HLS to compile the software functions Function1() and Function2() as written in C or C++ into FPGA hardware descriptions in VHDL or Verilog. However, the non-algorithmic elements of the design, such as interfaces, control, clocks, and resets could not be generated with HLS tools. Hardware designers would be needed to create these as custom IP. The job of sourcing those elements and connecting them poses yet another challenge, as some elements may not be readily available or may have different types or sizes of interfaces as well as different clocking requirements, specific start-up sequences, and so on.

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