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Save precious picoseconds with ECL-wired OR

23 Mar 2016  | Glen Chenier

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Usually, when you are designing with high-speed emitter-coupled logic (ECL), you have too little time between clock cycles to implement logic functions using gates between flip flops. In these cases, you can derive equivalent-logic functions using the wired-OR and flip flop complementary inverted outputs (reference 1, reference 2, and reference 3). You can parallel the emitter-follower outputs of ECL with a pulldown resistor to implement the OR function with almost no time-delay penalty. Complementary outputs—one inverted—provide delay-free logic inversions.

Figure 1: The XNOR comparison of inputs A and B results in too much propagation delay to guarantee setup at the final flip-flop’s input (a). The equivalent XNOR circuit uses NOR, AND, and OR gates (b), and OR gates and inverters realize the XNOR function (c). You can also implement the circuit using wired ORs (d) to eliminate the interflop XNOR-gate delay Aand almost double the usable clocking speed..

This Design Idea uses the older Motorola 10H ECL logic family, the fastest available when I was building the design (figure 1). Newer ECL families are much faster, but the same wired-OR principle applies. For clarity, the figure omits power and 50Ω pulldown resistors. This design needed an XOR comparison between a PRBS (pseudorandom-binary-sequence) data stream and a local PRBS reference for a BER (bit-error-rate) counter running at 250Mbit/s (figure 1a). A problem occurred with the design, however: The clock period at 250Mbit/s is 4 nsec, whereas the 10H107 XOR/XNOR gate's maximum propagation delay is 1.7 nsec. In addition, the 10H131 flip-flop's maximum propagation delay is 1.8 nsec, and the required input-setup time is 0.7 nsec. All these delays total 4.2 nsec, which exceeds the 4-nsec clock period by 200 psec. Adding a fourth flip-flop with wired-OR outputs to replace the 10H107 XOR/XNOR solves the problem (figure 1d).

The XNOR-equivalent function uses NOR, AND, and OR functions (figure 1b). The circuit in figure 1c separates the NOR into the equivalent OR with an output inverter and converts the AND into the equivalent OR with inverted inputs and output. Now, the circuit uses only ORs and inverters. This form is necessary for implementing the wired-OR equivalent (figure 1d). In this case, the inverted-complementary outputs of the flip-flops replace the inverters, and a parallel electrical connection between the flip-flops' outputs replaces the OR gates.

1. "Using Wire-OR Ties In ECLinPS Designs," Application Note AN1650/D, On Semiconductor.

2. "Dual D Type Master Slave Flip-Flop," MC10H131 Data Sheet, On Semiconductor.

3. "Triple 2-Input Exclusive OR/Exclusive NOR Gate," MC10H107 Data Sheet, On Semiconductor.

About the author
Glen Chenier contributed this article.

This article is a Design Idea selected for re-publication by the editors. It was first published on May 15, 2008 in

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