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Delayed-pulse generator uses dual flip-flop

30 Mar 2016  | Luca Bruno

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Some applications call for clock-timing adjustments, such as generating precision clocks for time-interleaved ADCs, or delay adjustments in a variety of precision-timing and pulse-delay applications. This design idea describes a delayed-pulse generator using a dual-CMOS D-type flip-flop (figure). The circuit provides precision time delays of a trigger-input pulse. A dc-control voltage selects a time delay within the full-scale range. When the rising edge of a pulse triggers the input, the circuit's output generates a pulse with its rising edge delayed by an amount equal to the selected time delay, TD, plus a fixed inherent propagation delay TPD. Also, a time constant, R4C2, determines the output pulse's width.

A precision dc source, IO, and capacitor C1 set the full-scale delay range. When Q3 is off, the current source charges capacitor C1, generating a linear-ramp voltage with slope equal to IO/C1. The delay is the time it takes for the ramp to rise from its initial voltage to the control-voltage value.

Figure: The rising edge of a trigger input starts a precision ramp voltage that compares with a control voltage, generating a precise delay.

In this application, the ramp slope is 10 mV/1µsec, so that the full-scale delay range is 256µsec for a control voltage of 0 to 2.56V. You can set the full-scale delay by changing IO through either R1+R2 or capacitor C1. For best accuracy, the current source can range from 10µA to 1 mA, the capacitor's value can range from 1 nF to 1µF, and the corresponding full-scale delay can range from 2.56µsec to 256 msec. Use a precision film capacitor for C1.

The basis of the current source is a shunt precision-micropower-voltage-reference, IC3, producing a reference voltage of 1.233V with an initial accuracy of 0.2%. A Texas Instruments LM4041, through precision resistors R1 and R2, biases the Darlington-coupled transistors Q1 and Q2 with a reference current IO=VREF/(R1+R2)=100µA. The Darlington configuration ensures that base current is negligible and that the output collector current can achieve a worst-case accuracy of 0.3%. You can use any small-signal transistor, but, for best accuracy, use high-gain, low-level, low-noise BJTs, (bipolar-junction transistors) such as a 2N5087 or a BC557C.

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