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Power precision SAR ADC with ultra-low power switcher

12 Apr 2016  | Alan Walsh

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Precision measurement is finding its way into application areas that require greater and greater power efficiency. This is particularly true with the advent of IoT, which is driving greater need for wireless sensor nodes with precision measurement capability, battery powered wearable fitness/medical devices and industrial signal chains that use isolated power, 4-20 ma loop powered or battery powered field instruments. In these scenarios greater power efficiency means longer battery lives with less maintenance as well as simplified power supply design.

Typically precision measurement systems use low-dropout regulators (LDOs) as part of their power supply schemes to generate low noise rails for precision ADCs. However LDOs can be very inefficient in delivering power and often the majority of power is lost in the LDO dissipated as heat. This article discusses a means of achieving a higher efficiency power solution for your precision successive approximation register (SAR) ADC. This is achieved by use of a ultra-low power switching regulator in a hysteretic mode and analysing the performance trade-offs including a means to intelligently control the switching regulator synchronous to the SAR conversion to improve noise performance.

Fixed frequency or pulse-width modulated (PWM) switching regulators provide a very efficient (often > 90%) means of generating voltage rails in a measurement system at medium to high load currents (100 mA's to A's). However this efficiency comes at the cost of switching ripple that is usually at a fixed frequency of 100'skHz to a couple of MHz. As can be seen in figure 1 the power supply rejection ratio, or PSRR, of a typical precision SAR ADC is very good at lower frequencies up to ~100kHz, beyond this the PSRR drops off rapidly.


Figure 1: SAR ADC Analogue Power supply rejection versus frequency.


This means that the ripple from fixed frequency or PWM switchers is not very well rejected and shows up at the ADC digital output. This can usually be seen in an FFT of the ADC output as a spur at the fixed frequency of the switcher. Moreover the efficiency of fixed frequency or PWM switchers tends to fall off rapidly at lighter load currents, e.g. <100 mA (figure 2).

Typical load currents to supply the VDD line of a precision SAR ADC are in the couple mAs range or uAs if the ADC is run at a lower throughput so there are no efficiency benefits in using a fixed frequency switcher to supply the ADC directly instead of an LDO.

However high efficiency, ultra-low power step-down switching regulators can be operated in a hysteretic mode with very low quiescent current.

In hysteresis mode, the regulator charges the output voltage slightly higher than its nominal output voltage with PWM pulses by regulating the constant peak inductor current. When the output voltage increases until the output sense signal exceeds the hysteresis upper threshold, the regulator enters standby mode. In standby mode, the high-side and low-side MOSFETs and a majority of the circuitry are disabled to allow a low quiescent current as well as high efficiency performance (figure 2). During standby mode, the output capacitor supplies energy into the load, and the output voltage decreases until it falls below the hysteresis comparator lower threshold. The regulator wakes up and generates the PWM pulses to charge the output again.

In this case the switching ripple frequency is a function of the load current and LC network and for loads of a couple mA's is in thekHz range. At a fewkHz the PSRR of the precision ADC is very good and will do a good job of rejecting/attenuating the switching ripple at the ADC digital output.


Figure 2: PWM (left) and Hysteretic mode (right) Efficiency versus load current.


Example ADC
Take for example the circuit shown in figure 3 with the AD7980 ADC. Its VDD current consumption is typically 1.5 mA at full throughput (1 MSPS) and scales linearly as you decrease the throughput. As can be seen in figure 4 the switching frequency ripple is 4.5kHz and 50 mV pk-pk on a 2.5V regulated output from a 5V rail. This ripple is attenuated at the ADC digital output by the PSRR rating of the ADC. In the ADC FFT output it shows up as a spur of magnitude -120 dBFS at 4.5kHz. For a 5V input range on the ADC this equates to


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