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Power precision SAR ADC with ultra-low power switcher

12 Apr 2016  | Alan Walsh

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The performance of the AD7980 @ 1 MSPS using the ADP5300 as the VDD supply is shown in figure 7 with a 10kHz almost fullscale input signal (-0.5 dB). The ADC still meets datasheet specification in terms of SNR (91.5 dB) and THD (-103 dB) however the ADP5300 switching ripple at 4.5kHz gets modulated on top of the input signal and appears as spurs at 10kHz – 4.5kHz (5.5kHz) and 10kHz + 4.5kHz (14.5kHz). These spurs are still at a very low level (-116 dBFS) and much less than the THD introduced by the second harmonic of the fundamental signal (-103.8 dBFS @ 20kHz). These artifacts are a small fraction of an lsb at the 16 bit level so in many applications will be perfectly acceptable for the power savings of the ADP5300 regulator.


Figure 7: Performance of AD7980 using ADP5300 as VDD supply. Side bands due to switching ripple modulation can be seen around the fundamental signal (10kHz ± 4.5kHz).


There is a STOP switching feature on the ADP5300 switcher that can completely eliminate these switching ripple artifacts from showing up in the ADC FFT output. The STOP pin on the ADP5300 prevents the SW pin from switching when STOP is held high. This can be used to prevent any switching from occurring during the noise sensitive conversion process of the ADC. In order to achieve this the CNV signal and STOP signal are tied together (figure 3) and the CNV signal from the processor is timed to remain high during the conversion time of the ADC (in the case of the AD7980 this is 710 ns max, conversion is initiated on CNV rising edge).

The results are shown in figure 8. The ripple frequency is more variable in this case as there are only specific times when the SW node can turn on and regulate. Also note that the SW turn on time from the STOP signal going low can be 100's of ns. In figure 8 the SW pin turns on ~850 ns after the falling edge of STOP. This means we cannot use the STOP feature at 1 MSPS ADC throughput as the VDD supply will fall out of regulation and collapse as there is insufficient time for the SW pin to go high and regulate. Instead the STOP function will work for throughputs of 500 kSPS and lower.


Figure 8: ADP5300 switching ripple (yellow) with STOP function at 500 KSPS throughput. CNV/STOP signal (blue). SW pin of ADP5300 (pink).


As can be seen in figure 9 the switching ripple spur is completely eliminated from the ADC noise floor with the use of the STOP signal. When an input signal of 10kHz is applied there is no modulation or artifacts around the fundamental apart from the normal harmonics. However there is an efficiency hit for using the STOP feature due to ringing on the SW pin when the SW pin is disabled (STOP high). The efficiency of the ADP5300 with an ADC throughput of 500kHz drops to ~75%. This is still considerably higher than the efficiency possible with an LDO (<50%) and gives the option of a power/performance trade-off that can be made in the application under the control of the processor/ucontroller if a separate control line is used for the STOP feature.


Figure 9: Performance of AD7980 using ADP5300 as VDD supply with STOP feature timed to conversion period.


The cost and PCB area of a switcher solution like the ADP5300 is comparable to that of an LDO. The main addition to the BOM is a chip inductor, a 2.2 uH inductor can be as small as 0603 size, with the input and output caps already being required for an LDO solution. This makes it an attractive alternative to using an LDO in power sensitive applications without significantly impacting precision performance.

High efficiency, ultra-low power switching regulators like the ADP5300 result in 45% power savings over LDOs when powering precision ADCs like the AD7980 from a 5V rail. This has touted benefits in IoT applications, extending battery life in wireless sensor nodes or wearable fitness devices, power sensitive isolated industrial systems and 4-20 ma loop powered systems.


About the author
Alan Walsh contributed this article.


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