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Boost QoR with new gen physical RTL synthesis

13 Apr 2016  | Arvind Narayanan

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The quality of the netlist generated during RTL synthesis has a massive impact on the rest of the physical design flow. For teams designing large SoCs at advanced nodes, it is more important than ever to come out of RTL synthesis with predictable timing and congestion estimates, DFT, and even a floorplan with good pin placements and feedthroughs. The quality of the netlist coming out of RTL synthesis has a big impact on the speed and predictability of the backend physical implementation and signoff.

What does quality of the netlist mean, and what are the bottlenecks of getting a good quality netlist for physical implementation? One barrier to better quality of results (QoR) from synthesis is when the synthesis tool optimises the design after generating gates from the RTL. For the best quality, designers need a high-capacity, physically-aware logic synthesis tool that optimises at a higher level of abstraction, not at the gate level. There are far more opportunities for QoR improvements when synthesis optimisation is performed at the RTL level.


Figure 1: Optimising at the RTL level offers more room for QoR improvement than gate-level optimisation, in addition to enabling higher capacity and faster runtimes.


However, there is a lack of physical information at the RTL level. Resorting to wire load models causes sub-optimal QoR metrics for timing and congestion. The answer is to perform placement before synthesis so that high-level optimisation can be performed at the RTL level instead of the gate level, as with traditional synthesis tools. The new RTL synthesis tool should be able to divide the RTL into virtual placeable partitions and then refine those down into actual library cells so that physical placement information is available at all times. A detailed netlist of each RTL partition should be used to accurately time the design. Each partition should be optimised and implemented as placed gates and if needed, the RTL should be repartitioned until all top-level design specifications are met. The placement and timing information should be dynamically updated with every optimisation transform. This will result in a very tight correlation between RTL synthesis and place and route for timing and congestion.

The second barrier to QoR is that restricted tool capacity forces designers to break down their chips into smaller blocks for synthesis, and then re-stitch during physical design implementation. Breaking the design into blocks that don't correspond to the physical hierarchy is a recipe for disaster as it is very difficult to get a good partition, and hard to budget timing constraints across the blocks. The problem with this block-level synthesis approach manifests as endless iterations when assumptions made in the synthesis tool, which can only see a single block at a time, are invalidated by the physical design tool when all the blocks are considered as a group. The design that emerges from place and route no longer satisfies its constraints resulting in a miscorrelation between front- end and back-end design flows. Particularly for large designs, RTL and physical engineers should look for a tool with the capacity to perform true chip-level synthesis and floorplanning. }

A side benefit of having high-quality physical RTL output is that it makes the entire design flow more predictable with shorter design cycles. Optimising at a higher level reduces RTL synthesis runtime, gives faster design convergence and cuts the time-consuming iterations. Using a high-level RTL physical synthesis solution with the capacity to handle 100+ million gate designs will deliver an enormous increase in productivity.

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