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Low-jitter multi-output clock IC has integrated VCO

31 Mar 2016  | Susan Nordyk

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Linear Technology has released the LTC6951, a low jitter Phase Locked Loop (PLL) multi-output clock synthesiser with a low-noise integrated VCO. The LTC6951 furnishes multiple clock outputs between 1.95 MHz and 2.7 GHz. It provides four CML (current mode logic) outputs, each equipped with an independent low-noise clock divider and digital delay block. A fifth output is low-noise LVDS.

With total absolute jitter of 115 fsRMS (ADC SNR method), the LTC6951 delivers the low-jitter clocks necessary to achieve the best SNR when clocking data converters with high input frequencies and fast output data rates. The device offers three intelligent schemes to simplify output clock expansion and the creation of large clock trees employed in systems with multiple daughter cards or with a large number of data converters.

The EZSync output-synchronisation method guarantees repeatable and deterministic phase relationships between all clock divider outputs of the LTC6951. ParallelSync multichip parallel synchronisation allows the outputs of multiple LTC6951 ICs to be retimed to the common reference clock. Finally, a JESD204B subclass 1 compliant synchronisation method enables the generation of the SYSREF and DEVCLK signals across multiple parallel connected LTC6951 ICs, along with any other EZSync-compatible clock devices.

Housed in a 5×7-mm, 40-lead plastic QFN package, the LTC6951 costs $8.75 each in lots of 1000 units.

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