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Lattice increases on-chip memory with expanded family of FPGAs

22 Apr 2016  | Julien Happich

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Due to consistent client demand, Lattice semiconductors expanded I/O and logic support for control PLD applications, while increased on-chip memory improves picture clarity for low cost video bridging in large monitor applications. The MachXO3 family aims to target the server, communications, industrial and display markets.


Figure 1: Lattice claims logic support for control PLD applications with MachXO3LF-9400.

The new enhanced features of the MachXO3 family make it ideally suited for implementing control path functions. These include a glue-less 1V I/O interface for out-of-band communication with new, leading-edge processors; hitless I/O enables in-system hardware upgrade along with a switch over from its old configuration to the newly programmed configuration without interrupting the circuit board operation; password protection makes the system more robust against malicious erase commands. The SED/SEC/SEI feature enables recovery from a soft error event in milliseconds. Adding analogue I/Os is simple and enables integration of all hardware management while reducing overall cost. Fast 900Mbit/s operating speeds supported by MachXO3-9400 FPGA's I/Os ensures that even high-resolution video streams operate smoothly.

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