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Minimising FPGA debug time

29 Apr 2016  | Joe Mallet

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FPGA device density is continuously increasing at approximately 2x per node, which is driving the ability for FPGAs to incorporate more of the system design into the devices. This means that companies designing new FPGA-based products continue to drive higher integration and, subsequently, more complexity into their system designs. This has led companies designing complex FPGAs to move increasingly towards licensing IP cores for the majority of the building blocks of their designs, as opposed to building their own in-house custom versions.

FPGA designers typically use IP from multiple sources ranging from internal to FPGA device vendors. In order to efficiently leverage IP from multiple sources, designers require synthesis and debug tools that support the portability of IP across technologies, along with the ability to properly handle the various forms of IP. The Synplify synthesis tools automate much of the handling of design IP by directly supporting vendor IP catalogs like Altera's Megawizards and Xilinx's IP catalogue.


Figure 1: Example IP flows for FPGA vendor tools (Source: Synopsys).


In addition to the automated and correct handling of IP, the debug of complex FPGA designs with multiple sources of IP is challenging to FPGA designers. When the design fails to operate as expected, the FPGA designer has to determine what is causing the issue, which is only made harder if the design is developed by multiple teams worldwide. Distributed FPGA design development is creating a need to isolate and fix errors quickly throughout the design cycle. While FPGA vendors provide on-chip logic debuggers, they have limited visibility and traceability back to the RTL design. In addition, each change in the watched nodes requires a new recompile causing more time delays.


Figure 2: Example real-time device values mapped back into the RTL for complete visibility into the design (Source: Synopsys).



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