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Hardware emulation flexibility makes big impact on ROI

29 Apr 2016  | Lauro Rizzatti

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The Design Automation Conference is just around the corner and verification teams are starting to make their "must see" lists of vendors. Paramount among their choices has to be hardware emulation providers since this is the tool leading verification strategies nowadays. In fact, hardware emulation is extensively considered the universal verification tool that can be used across the SoC development cycle.

And, little wonder, because hardware emulation is widely considered the universal verification tool that can be used throughout the SoC development cycle. It can map any design size, even in excess of a billion gates, and it gives users full design visibility for thorough hardware debugging. In virtue of its six orders of magnitude speedup versus RTL simulators, it can validate embedded software, including drivers, operating systems, diagnostics and applications. In fact, it is used extensively to debug processors, graphics, multimedia, networking, storage, automotive designs and practically any other digital design.

The return on investment (ROI) analysis has to be significant for engineering managers and accountants alike.

Let's consider... Today's engineering teams are composed of both hardware engineers and software developers because software and hardware are being produced simultaneously. Both groups have come to value hardware emulation's ability to verify concurrently hardware and software. Because the emulated design is based on an actual silicon implementation, albeit not timing-accurate, it offers an accurate functional representation of the design before the silicon is ready for testing. This is critical to trace bugs, even software bugs that propagate through the hardware. Its value is quantifiable and justifiable.

Hardware emulator deployment

Over time, the deployment of hardware emulators has changed. The change has been accelerated by the need for a more accommodating test environment than the long-relied-upon in-circuit emulation (ICE) mode. In ICE mode, which is still in use but waning in popularity, a physical target system, where the design under test (DUT) will reside once it's taped out, provides stimulus and processes the response.

The change has come in the form of virtual target systems driving the DUT via interfaces implemented by transactors, synthesisable software models of protocol interfaces. These transactors communicate with the virtual target system through an untimed packet of information and with the DUT using bit-level signals. Since transactors can be mapped inside the hardware emulator, they execute at the maximum speed of the emulator. In transaction-based verification, users describe the virtual test environment or testbench at a higher level of abstraction using at least one order of magnitude less code than in conventional hardware verification language (HVL) testbenches.

Transaction-based emulation is attractive to many engineering teams and semiconductor companies because it doesn't require an on-call technician. This is handy when a remote user logs in, or if another user needs to swap designs, because no manual intervention is needed to plug or unplug speed adapters.

While ICE mode verifies the DUT with real traffic, new developments like VirtuaLAB effectively replace the ICE physical testbench with a functionally equivalent virtual testbench, thereby removing one of the few remaining obstacles for using it.

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