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Comparing HDL coding styles

03 May 2016  | Adam Taylor

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The major differences among coding styles relate to how the design engineer decides to handle VHDL keywords and any user-defined items (the names of signals, variables, functions, procedures, etc.). Although there are many different possibilities, in practice there are only three commonly used approaches. The first technique is to use a standard text editor and simply enter everything in lowercase (and black-and-white) as shown in the following example of a simple synchroniser:


B&W: Keywords and user-defined items in lowercase.


The second method is to follow the VHDL Language Reference Manual (LRM), which says that keywords (if, case, when, select, etc.) should be presented in lowercase. Strangely, the LRM doesn't have anything to say about how user-defined items should be presented, but the common practice (when the keywords are in lowercase) is to present user-defined items in uppercase as shown below:


B&W: Keywords lowercase; user-defined items uppercase.


The third approach—and my personal preference—is to turn the LRM on its head; to capitalise keywords (IF, CASE, WHEN, SELECT, etc.) and to present any user-defined items in lowercase as shown below:


B&W: Keywords uppercase; user-defined items lowercase.


The main argument for using uppercase for keywords and lowercase for user-defined items, or vice versa, is that this helps design engineers and reviewers to quickly locate and identify the various syntactical elements in the design. However, this line of reasoning has been somewhat negated by the use of today's context-sensitive editors, which are language-aware and therefore able to automatically assign different colours to different items in the design.

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