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Comparing HDL coding styles

03 May 2016  | Adam Taylor

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Let's look at our original examples through the "eyes" of a context-sensitive editor as illustrated in the following three images:

Colour: Keywords and user-defined items in lowercase.

Colour: Keywords lowercase; user-defined items uppercase.

Colour: Keywords uppercase; user-defined items lowercase.

Although context-sensitive editors are extremely efficacious, it's important to remember that some users may be colour-blind. Also, even if the code is captured using a context-sensitive editor, it may be that some members of the team end up viewing it using a non-context-aware (black-and-white) editor. Furthermore, the code may well be printed out using a black-and-white printer. For all these reasons, my personal preference is to capitalise keywords and for everything else to be in lowercase.

Aside from how we handle the keywords, most companies will have their own sets of coding guidelines, which will also address other aspects of coding, such as:

 • Naming conventions for clock signals; possibly requiring each clock name to include the frequency, e.g., clk_40MHz, clk_100MHz.

 • Naming and handling of reset signals to the device (active-high, active-low), along with the synchronisation of the signal and its assertion and de-assertion within the FPGA. The de-assertion of a reset is key, as removing this signal at the wrong time (too close to an active clock edge) could lead to metastability issues in flip-flops.

 • Naming conventions for signals that are active-low (this is common with external enables). Such signals often have a "_z" or "_n" attached to the end, thereby indicating their status as active-low ("ram_cs_n" or "ram_cs_z," for example).

 • The permissible and/or preferred libraries that will ensure the standard types that can be used. Commonly used libraries for any implementable code are "std_logic_1164" (this is the base library that everyone uses) and the "numeric_std" for mathematical operations (as opposed to "std_logic_arith"). Meanwhile, other libraries such as "textio" and the "math_real" and "math_complex" libraries will be used when creating test benches.

 • The use of "std_logic" or the unresolved "std_ulogic" types on entities and signals ("std_ulogic" is the unresolved type of "std_logic" and is used to indicate concurrent assignments on a signal).

 • Permissible port styles. Many companies prefer to use only "in," "out," and "inout" (for buses only) as opposed to "buffer," as the need to read back an output can be handled internally with a signal. Also, many companies may limit the types permissible in entities to just "std_logic" or "std_logic_vector" to ease interfacing between large design teams.

 • It is also common for companies in some specialist safety-critical designs to have rules regarding the use of variables.
These coding styles can be very detailed, depending upon the end application the FPGA is being developed for. What coding style and standards do you use?

About the author
Adam Taylor is a Chief Engineer—Electrical Systems at E2V. He was previously the Head of Electronic Design at Europe's leading Space company Astrium, where he had a dual role as Head Of Electronic Design and a Responsible Engineer leading product development. In this role he lead the development of the latest generation of space-based telecommunications processors based around the Virtex 5 QV and Deep Subµm ASIC technology. He has spent the last 13 years developing both hardware and FPGA solutions for telecommunications, cryptographic, radar, safety critical systems, and thermal imaging systems, among others. Having worked with reliable design techniques for many years, he is formalizing his experiences and knowledge in book that he is currently writing. He is a Chartered Engineer and a Fellow of the Institute of Engineering and Technology.

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