Path: EDN Asia >> Design Ideas >> IC/Board/Systems Design >> Controlling FPGA bus without using processor
IC/Board/Systems Design Share print

Controlling FPGA bus without using processor

10 May 2016  | Noe Quintero

Share this page with your friends

Many FPGA designs employ an embedded processor for control. A typical solution involves the use of a soft processor such as a Nios, though FPGA SoCs with a built-in hard processor have become popular too. Figure 1 shows a typical Altera FPGA system that contains the processor and a mix of peripherals that are connected via Altera's Avalon Memory Mapped (MM) bus. These processors greatly simplify the end application, but require a strong programing background and knowledge of complicated toolchains. This can hinder debug, especially if a hardware engineer needs a simple way to read and write to the peripherals without pestering the software engineer.


Figure 1: Typical Altera FPGA system connected using the Avalon memory-mapped bus.


This Design Idea uses Altera's SPI Slave to Avalon MM Bridge to provide a simple way to hop onto the Avalon bus. There are two advantages to this technique: It does not compromise the original system design, and the bridge can co-exist with the embedded processor. For the system shown in figure 1, the SPI bridge allows the engineer to directly control the frequency of the LTC6948 fractional-N PLL, set the LTC1668 DAC voltage, read a voltage from the LTC2498 ADC, or read temperatures from the LTC2983, just like the processor can.



Figure 2: Highlighter + Example code + Reverse engineering = Python script (zoomable images).


Altera provides a reference design for the SPI-Avalon MM bridge. Unfortunately, the documentation is sparse at best, and uses a Nios processor as the SPI master. This effectively defeats the purpose of the SPI bridge, as the Nios can interface directly to the Avalon MM bus. A practical SPI master is Linear Technology's Linduino microcontroller, which is an Arduino clone with extra features to interface to LT demo boards. One extra feature is a level-shifted SPI port. This level-shifting function is especially helpful when interfacing to FPGA I/O banks with voltages as low as 1.2V. The Linduino firmware can be used to accept commands through a virtual COM port and translate the commands to SPI transactions.

After reverse engineering the Altera example design (the left side of figure 2), a Python library was developed to create packets that the bridge would accept. These packets are then translated into Linduino commands. A Python script then allows the hardware engineer to have complete control of the project without needing to reinvent the interfacing protocols. An example Python script to control the frequency of a digital pattern generator for an LTC1668 DAC is provided in the LinearLabTools Python folder. Figure 3 shows the demo setup.


Figure 3: DC2459 DAC demo board (R) plugged into an FPGA board (L).



1 • 2 Next Page Last Page


Want to more of this to be delivered to you for FREE?

Subscribe to EDN Asia alerts and receive the latest design ideas and product news in your inbox.

Got to make sure you're not a robot. Please enter the code displayed on the right.

Time to activate your subscription - it's easy!

We have sent an activate request to your registerd e-email. Simply click on the link to activate your subscription.

We're doing this to protect your privacy and ensure you successfully receive your e-mail alerts.


Add New Comment
Visitor (To avoid code verification, simply login or register with us. It is fast and free!)
*Verify code:
Tech Impact

Regional Roundup
Control this smart glass with the blink of an eye
K-Glass 2 detects users' eye movements to point the cursor to recognise computer icons or objects in the Internet, and uses winks for commands. The researchers call this interface the "i-Mouse."

GlobalFoundries extends grants to Singapore students
ARM, Tencent Games team up to improve mobile gaming


News | Products | Design Features | Regional Roundup | Tech Impact