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Controlling FPGA bus without using processor

10 May 2016  | Noe Quintero

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Many FPGA designs employ an embedded processor for control. A typical solution involves the use of a soft processor such as a Nios, though FPGA SoCs with a built-in hard processor have become popular too. Figure 1 shows a typical Altera FPGA system that contains the processor and a mix of peripherals that are connected via Altera's Avalon Memory Mapped (MM) bus. These processors greatly simplify the end application, but require a strong programing background and knowledge of complicated toolchains. This can hinder debug, especially if a hardware engineer needs a simple way to read and write to the peripherals without pestering the software engineer.

Figure 1: Typical Altera FPGA system connected using the Avalon memory-mapped bus.

This Design Idea uses Altera's SPI Slave to Avalon MM Bridge to provide a simple way to hop onto the Avalon bus. There are two advantages to this technique: It does not compromise the original system design, and the bridge can co-exist with the embedded processor. For the system shown in figure 1, the SPI bridge allows the engineer to directly control the frequency of the LTC6948 fractional-N PLL, set the LTC1668 DAC voltage, read a voltage from the LTC2498 ADC, or read temperatures from the LTC2983, just like the processor can.

Figure 2: Highlighter + Example code + Reverse engineering = Python script (zoomable images).

Altera provides a reference design for the SPI-Avalon MM bridge. Unfortunately, the documentation is sparse at best, and uses a Nios processor as the SPI master. This effectively defeats the purpose of the SPI bridge, as the Nios can interface directly to the Avalon MM bus. A practical SPI master is Linear Technology's Linduino microcontroller, which is an Arduino clone with extra features to interface to LT demo boards. One extra feature is a level-shifted SPI port. This level-shifting function is especially helpful when interfacing to FPGA I/O banks with voltages as low as 1.2V. The Linduino firmware can be used to accept commands through a virtual COM port and translate the commands to SPI transactions.

After reverse engineering the Altera example design (the left side of figure 2), a Python library was developed to create packets that the bridge would accept. These packets are then translated into Linduino commands. A Python script then allows the hardware engineer to have complete control of the project without needing to reinvent the interfacing protocols. An example Python script to control the frequency of a digital pattern generator for an LTC1668 DAC is provided in the LinearLabTools Python folder. Figure 3 shows the demo setup.

Figure 3: DC2459 DAC demo board (R) plugged into an FPGA board (L).

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