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Controlling FPGA bus without using processor

10 May 2016  | Noe Quintero

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Figure 4 shows the system block diagram. Note that the numerically controlled oscillator (NCO) can be controlled by the shift register or the PIO core. The shift register is included for debug, as it allows direct control of the NCO. Setting the GPIO line high enables the SPI-Avalon bridge, which in turn controls a 32bit PIO port over the Avalon bus. The PIO output then controls the NCO frequency.


Figure 4: FPGA system block diagram.


With the basic system operational, additional peripheral cores can be connected to the bus. To design the system, Altera provides a tool called Qsys, which provides a GUI to connect the IPs to one another. Qsys translates the GUI-designed system (figure 5) to HDL. Peripheral addresses are fully configurable. In this case, the PIO is set to a base of 0x0.


Figure 5: Qsys GUI.


Once the design is implemented in the FPGA, the provided Python library in LinearLabTools contains two functions to interface to the design:

transaction_write(dc2026, base, write_size, data)

transaction_read(dc2026, base, read_size)

The first argument to these functions is the Linduino serial port instance. The second argument is the peripheral's address on the Avalon bus. The functions accept and return lists of bytes respectively. These two functions are written to allow flexibility when writing and reading to IP. To set the NCO for the provided example, the transaction_write function is all is needed. Equation 1 is used to determine the tuning word.



To set the NCO to 1kHz with a 50MSPS sample rate, the tuning value is 85899, or 0x00014F8B, which is passed as a list of four bytes. Thus, the python code to set the DAC to 1kHz is:

transaction_write(linduino_serial_instance, 0, 0, [0x0, 0x01, 0x4F, 0x8B])



Figure 6: Python Avalon bus example.


The Python script in figure 6 illustrates the simple text interface that configures the NCO. An important note: the bridge uses SPI mode 3. This was painfully determined to be the correct mode by trial and error, and verified by analysing the Nios processor's SPI interface in Altera's example.

This design idea provides the ability to control a system without touching the embedded processor, allowing the hardware engineer to progress on a project without bothering the software engineer, and with minimal impact to the hardware design.


About the author
Noe Quintero is an Associate Application Engineer in the Mixed Signal group at Linear Technology. He joined the company in 2012 as an intern, and started full time in 2015. Noe has a BS in Electrical Engineering from San Jose State University. He has an identical twin, who is also in the EE field. Noe's hobbies includes, cycling, building robots, and saltwater reef aquariums.


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