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Three prophecies for high speed serial link systems

10 May 2016  | Eric Bogatin

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The DesignCon this year brought to light insights pertaining to the future of signal integrity. Consequently, I have three predictions about major changes ahead for high speed serial link systems.

Roll out of 28Gbit/s systems will be slower than expected.

I hear that the semiconductor companies producing the CMOS devices (ASIC, FPGA or custom) are doing fine producing the silicon with acceptable performance at 28Gbit/s.

Silicon with 28Gbit/s signal

Figure 1: Today's silicon can produce clean signals at 28Gbit/s, at least at the transmit end.

Semiconductor manufacturers' ability to sell to end users designing and manufacturing systems operating with 28Gbit/s links is, however, limited by the their ability to support these customers.

A link operating at 28Gbit/s, NRZ (non-return-to-zero), has to be designed with everything working almost perfectly. This data rate pushes the limits such as: low Df materials, smoother copper, wide enough lines, equalisation tuned to the limit of recovering -25dB of insertion loss, minimal reflections, via stubs shorter than 15 mils, channel-to-channel cross talk less than -50dB, and line-to-line skew less than 6ps over as long as 20in.

By themselves, each item is possible to engineer, but all of them at the same time in the same channel requires solid engineering and analysis. Not every design team is capable of this task. When the channel does not work, who do they call? The silicon provider.

I hear that with a limited number of experienced support application engineers, the silicon providers are focusing on their large, high-end OEM customers and are limiting their sales based on which customers they have the resources to support. This may be a business opportunity for consulting engineering teams to work with silicon providers to support their customers and increase the design wins and sales of 28Gbit/s capable silicon.

There is a potential roadblock ahead for 56Gbit/s PAM4 systems.

A number of channels have been demonstrated operating at 56Gbit/s with PAM4. The picks and shovels needed for PAM4 systems are in place. Most of the high-end software vendors have shown design tools for simulating PAM4. All the high-end oscilloscope and BERT (bit-error-rate tester) manufacturers have shown instruments able to measure and characterise PAM4 systems.

PAM4 signal

Figure 2: At the transmitter, a PAM4 signal is clean enough for all three eyes to be visible.

It's widely believed that the advantage of going to PAM4 for 56Gbit/s is so that we are only dealing with signals with an equivalent bandwidth of 28Gbit/s signals. If we can design a channel for 28Gbit/s at PAM2, we should be able to design one for 56Gbit/s at PAM4.

Not so fast, for there is one significant difference with PAM4. By dividing up the signal into three levels plus zero, we dropped the signal level for one bit by 1/3. The signal voltage level we have to measure is smaller. If we need a particular SNR (signal-to-noise ratio) at the receiver for an NRZ-PAM2 signal, and the signal level dropped by 10dB, the acceptable noise level has to drop by 10dB in PAM4. But wait, we're not done.

In NRZ-PAM2, we need about -50dB isolation between a channel and all other aggressors for a SNR of 20dB. With a lower noise floor required in PAM4, this means an isolation of -60dB. When it comes to cross talk, we still have high level signals corresponding to the fourth bit level sometimes coming out of the TX. This means the signal on the aggressor can be 3x higher than the signal of the second bit. To keep the same noise on the victim line when the aggressor has 10dB higher strength, we need another 10dB more isolation. This means an isolation of as low as -70dB between the victim channel and all other aggressor channels.

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