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PCB design: Managing power integrity analysis bottleneck

19 May 2016  | John Carney

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Is your PCB design team using up too much time waiting for IR-drop analysis results on the power delivery network (PDN), or trying to optimise the decoupling capacitor network without under- or over-designing it? Given the miniscule voltages of today's designs, there's really no margin for error in the PDN. How can PCB designers gain useful IR-drop insights quickly from overloaded power integrity (PI) engineers so they can meet stringent time-to-market targets? In this article, we'll discuss technology that empowers PCB designers with fast access to the same trusted, comprehensive, and accurate IR-drop analysis functions used by the analysis experts.

Ensuring sufficient power delivery in a PCB design, without requiring excess layers or larger board size, is essential. IR-drop analysis has, however, become quite challenging. With low-power design, core voltage levels have continued to drop—1.5V or less is now common. As voltage is reduced, current requirements typically increase. At the same time, miniaturisation of electronics means fewer layers and higher densities—so, less available area for power nets.

There needs to be a faster, more reliable way for IR-drop analysis results to get into the hands of PCB designers, so they can properly manage the power flow through the PDN in their designs and meet aggressive time-to-market goals.

PDN challenges in PCB design
Because IR-drop analysis is a specialised skill, PCB designers typically face some frustrating PDN challenges. Often, the PCB designer must interpret multiple instructions—by email or verbally—from the PI engineer, applying these directions to multiple power rails and ICs. The designer must also balance various other system requirements in a tight timeframe.

Indeed, the communication flow between PCB designers and PI engineers creates some of these challenges. If yours is like a typical organisation, there are several PCB designers for every PI engineer. With multiple ongoing projects, the PI engineer must juggle simultaneous demands for time-consuming IR-drop analysis work. Given this queue of work, PCB designers aren't able to get instant IR-drop analysis results. So, the PCB designer ends up having to wait for initial analysis results and then waiting some more while going back and forth with the PI engineer for additional analysis after every adjustment to the design.

In addition, there hasn't been a formal process to tell the designer exactly how much metal to add to their board in response to the IR-drop analysis results. Nor has there been a way to indicate whether enough metal has been added for every power rail in the PCB design. That's why timely analysis and guidance on the adjustments that need to be made are necessary.

Good vs. bad PDN designs
Figure 1 shows an example of a bad PDN design. The scale on the right shows voltage from 1.46V down to 1.25V. The large ICs on the left side of the design are only getting 1.25V, which is far below an acceptable tolerance level.

Figure 1: A PDN design with circuitry that isn't getting enough power.

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