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PCB design: Managing power integrity analysis bottleneck

19 May 2016  | John Carney

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Similarly, look at the plot in figure 2 showing via current. The colour scale on the right shows vias in the design with over 8 amps of current flowing through them—far above tolerance. Checking a design with thousands of vias could be a staggering task. Therefore, designers need to be able to apply PI constraints that define the acceptable level for voltage and current, and report specific design instances that violate the constraints.

Figure 2: Vias with too much current.

Figure 3 shows an example of a better PDN design. The scale on the right shows voltage from 1.49V down to 1.43V. In this case, the large ICs on the left of the design are getting 1.43V, which is much better than what was happening in figure 1.

Figure 3: A PDN design showing good levels of current flow.

Looking at the via current in this design, the maximum is now 1.59 amps, vs. over 8 amps in figure 2 because many more vias were added to the design (figure 4).

Figure 4: Another view of the PDN design, where the maximum via current is 1.59 amps.

Bridging the gap between IR-drop analysis and PCB design
Technology that makes the best use of the unique skill sets of PCB designers and PI engineers and that drives faster access to power delivery insights is essential. An ideal solution would first enable the PI engineer to manage the complex setup of the analysis technology and allow the designer to reuse the setup parameters. With this approach, the designer could run and rerun the analysis to gather data while resolving first-order problems. Afterwards, the designer could hand the design over to the PI engineer, who would use the same models and report files, reducing the number of iterations.

Other useful capabilities to look for in a solution include:

 • Cross-probing between layout design and analysis results, so the designer can use visual analysis results to determine whether they need to increase the size of the power shapes, add vias, add planes, or make any other changes to the PCB.
 • DRC markers from analysis annotated to layout, which would help the designer understand and address issues discovered by the PI engineer.

Another important part of PDN design is the ability to devise a decoupling capacitor scheme that balances cost versus performance. Large ICs switch at fast speeds. When a whole address bus switches from high to low, it will draw from the power supply, causing the voltage level to drop. Typically, this happens faster than the PCB power supply can respond. To compensate, decoupling capacitors can be added near the power pins on the IC. When the IC switches logic levels, the capacitor discharges in reaction to the voltage change across its terminals, correcting the drop in supply voltage. The images in figure 5 show an example. In the top image, some data waveforms appear with an ideal 1.5V power supply. Unfortunately, in reality, this doesn't happen. The image on the bottom illustrates what really happens: the switching of the logic signals causes noise in the reference power supply, degrading the quality of the data.

Figure 5: Switching of logic signals causes noise in the reference power supply, which degrades the quality of the data.

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